74ALVCH16646 View Datasheet(PDF) - Philips Electronics
Part Name
Description
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74ALVCH16646 Datasheet PDF : 12 Pages
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Philips Semiconductors
16-bit bus transceiver/register (3-State)
Product specification
74ALVCH16646
FEATURES
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through pin-out architecture
• Low inductance, multiple VCC and ground pins for minimum noise
and ground bounce
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• Output drive capability 50Ω transmission lines @ 85°C
• All inputs have bushold circuitry
DESCRIPTION
The 74ALVCH16646 consists of 16 non-inverting bus transceiver
circuits with 3-State outputs, D-type flip-flops and control circuitry
arranged for multiplexed transmission of data directly from the
internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the
internal registers, as the appropriate clock (CPAB or CPBA) goes to a
HIGH logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and SBA)
can multiplex stored and real-time (transparent mode) data. The
direction (DIR) input determines which bus will receive data when
OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’ data
may be stored in the ‘B’ register and/or ‘B’ data may be stored in the
‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
PIN CONFIGURATION
1DIR 1
1CPAB 2
1SAB 3
GND 4
1A0 5
1A1 6
VCC 7
1A2 8
1A3 9
1A4 10
GND 11
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
GND 18
2A3 19
2A4 20
2A5 21
VCC 22
2A6 23
2A7 24
GND 25
2SAB 26
2CPAB 27
2DIR 28
56 1OE
55 1CPBA
54 1SBA
53 GND
52 1B0
51 1B1
50 VCC
49 1B2
48 1B3
47 1B4
46 GND
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
39 GND
38 2B3
37 2B4
36 2B5
35 VCC
34 2B6
33 2B7
32 GND
31 2SBA
30 2CPBA
29 2OE
SY00011
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CPD
Propagation delay
nAx to nBx
Input capacitance
Power dissipation capacitance per channel
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
Outputs enabled
Outputs disabled
Fmax
Maximum clock frequency
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
TYPICAL
2.6
2.7
3.0
36
4
300
320
UNIT
ns
pF
pF
MHz
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH16646 DGG
NORTH AMERICA
ACH16646 DGG
DWG NUMBER
SOT364-1
1998 Sep 03
2
853-2116 19959
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