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ST10F269 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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ST10F269 Datasheet PDF : 160 Pages
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ST10F269
Symbol
P4.0 –P4.7
RD
WR/WRL
READY/
READY
ALE
EA
Pin
85-92
85
86
87
88
89
90
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92
95
96
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98
99
Type
Function
I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output
via direction bit. Programming an I/O pin as input forces the corresponding output
driver to high impedance state. The input threshold is selectable (TTL or special).
Port 4.6 & 4.7 outputs can be configured as push-pull or open drain drivers.
In case of an external bus configuration, Port 4 can be used to output the segment
address lines:
O P4.0 A16
Segment Address Line
O P4.1 A17
Segment Address Line
O P4.2 A18
Segment Address Line
O P4.3 A19
Segment Address Line
O P4.4 A20
Segment Address Line
I
CAN2_RxD CAN2 Receive Data Input
O P4.5 A21
Segment Address Line
I
CAN1_RxD CAN1 Receive Data Input
O P4.6 A22
Segment Address Line
O
CAN1_TxD CAN1 Transmit Data Output
O P4.7 A23
Most Significant Segment Address Line
O
CAN2_TxD CAN2 Transmit Data Output
O External Memory Read Strobe. RD is activated for every external instruction or data
read access.
O External Memory Write Strobe. In WR-mode this pin is activated for every external
data write access. In WRL mode this pin is activated for low Byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
I Ready Input. The active level is programmable. When the Ready function is
enabled, the selected inactive level at this pin, during an external memory access,
will force the insertion of waitstate cycles until the pin returns to the selected active
level.
O Address Latch Enable Output. In case of use of external addressing or of multi-
plexed mode, this signal is the latch command of the address lines.
I External Access Enable pin. A low level applied to this pin during and after Reset
forces the ST10F269 to start the program from the external memory space. A high
level forces the MCU to start in the internal memory space.
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