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S4806CBI View Datasheet(PDF) - Unspecified

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S4806CBI Datasheet PDF : 4 Pages
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S4806CBI: OHIO
Product Brief Version 1.3 - April 2001
STS-48/STM-16 SONET/SDH Framer and ATM/POS Mapper
Overview and Applications
The S4806 - OHIO is a highly-integrated STS-48/STM-16 SO-
NET/SDH framer and POS/ATM mapper IC.
The line interface can process either a single STS-48/STM-16
or four STS-12/STM-4 signals carrying a mix of ATM, packet or
TDM traffic. The S4806 integrates a STS-1 level cross-connect
that allows to drop traffic through a dedicated expansion TDM
port. Alternatively, the TDM drop port can be used as a second
SONET/SDH-compliant line interface to support APS between
two OHIO devices or two fiber optics modules.
The S4806 also performs full Path Overhead (POH) generation
and monitoring as well as full-duplex mapping of packets, cells
or directly mapped traffic into tributaries ranging from DS3 over
STS-1/AU-3 to STS-48c. Up to 48 tributaries can be processed
simultaneously.
For packets or cell transfers on the system bus, the Flexbus-
3TM system interface supports multiple configurations, including
UTOPIA 3 and OIF SPI-3 modes.
The high level of integration, versatility and depth of channeliza-
tion of the S4806 - OHIO make it a perfect fit for aggregation
edge equipment as well as multi-service switches.
SONET Processing
The S4806 implements SONET/SDH processing functions for
STS-48/STM-16 or four STS-12/STM-4 data streams. It can
support any combination of STS-48c/AU-4-16c, STS-12c/AU-4-
4c, STS-3c/AU-4, and/or STS-1/AU-3 signals within an STS-48/
STM-16, or any combination of STS-12c/AU-4-4c, STS-3c/AU-
4 or STS-1/AU-3 signals within the STS-12/STM-4 data
streams. The S4806 provides full section, line and path over-
head processing of all defined TOH/POH bytes, including fram-
ing, scrambling/descrambling, alarm signal (AIS) insertion/
detection, remote failure indication insertion/detection (RDI/
REI), and bit-interleaved parity (BIP) processing. The OHIO
provides programmable Signal Fail (SF) and Signal Degrade
(SD) thresholds for each line and path interface.
The S4806 is SONET and SDH standards compliant with
Bellcore GR-253 and GR-499, ANSI T1.105 and ITU G.707 and
G.783.
ATM Processing
The S4806 can be configured for ATM processing on a per trib-
utary basis. The S4806 can terminate up to 48 data tributaries
carrying ATM cells , with data rates anywhere from STS-48c/
AU-4-16c down to STS-1/AU-3.
Cells received from or sent to the system interface can be either
52 or 56 bytes long
Transmit ATM Processor
In the transmit direction, the S4806’s ATM processor will per-
form all necessary cell encapsulation including optional HEC
generation, cell payload scrambling (X43+1), and idle cell inser-
tion to adapt the cell rate to the SPE or DS3 frame rate.
When mapping into DS3 frames, cells are either nibble-aligned
with DS3 multiframes or encapsulted in PLCP frames before
being mapped into the DS3 frame.
ADVANCED PRODUCT BRIEF
Receive ATM Processor
When receiving data from the line side, it performs cell delinea-
tion, HEC checking, descrambling, and receive cell rate adapta-
tion by discarding idle cells.
The S4806 is ATM standards compliant with ATM Forum UNI
3.1, ITU-T I.432.1 and I.432.2.
POS HDLC Processing
The S4806 can be configured for POS HDLC processing on a
per tributary basis. The S4806 can terminate up to 48 data trib-
utaries carrying packet traffic, with data rates anywhere from
STS-48c/AU-4-16c down to STS-1/AU-3.
Byte-stuffed HDLC processor (POS mode)
In Packet Over SONET mode, the S4806’s transmit HDLC pro-
cessor will provide the insertion of HDLC framed packets into
the Synchronous Payload Envelope. It optionally inserts provi-
sionned Address and Control fields and generates a 16 or 32 bit
FCS. It also performs transparency processing, optional pay-
load scrambling (X43+1) and inter-frame time fill.
The receive HDLC processor provides for the delineation of
HDLC frames, de-scrambling (if enabled), transparency
removal and FCS error checking. The HDLC Address and Con-
trol fields are optionally checked and can be either dropped or
passed-through the system interface. The S4806 also provides
a robust set of counters and status/control registers for perfor-
mance montoring via the microprocessor.
Bit-stuffed HDLC processing (DS3 mode)
For packet over DS3, the S4806 supports bit-stuffed HDLC
mapping and demapping of packets into DS3 frames. Transpar-
ency processing is performed by adding a ‘0’ after each
sequence of five contiguous ‘1’ and packets are then mapped
bit-by-bit into the DS3 frame. For each frame, a FCS is com-
puted, appended to the frame and transparency processed.
During inter-frame fill time, the flag sequence is normally trans-
mitted but the S4806 can optionally be provisioned to transmit
15 or more mark idle bits as required by some circuit-switched
links.
The receive bit-stuffed HDLC processor performs removal of
inter-frame flags, transparency processing and FCS checking.
The S4806 is POS/HDLC standards compliant with IETF RFC
1662/2615. Additionally, the S4806 HDLC processor support IP
and Ethernet mapping over SONET/SDH using Link Access
Procedure -SDH (LAPS) as proposed by ITU X.85 and X.86.
Direct Map Mode
The S4806 provides with the ability to directly map the traffic
received from the Flexbus-3TM system interface into the Syn-
chronous Payload envelope (SONET/SDH tributaries) or DS3
frames (DS3 over STS-1/AU-3 mode). In this mode, the ATM
and HDLC processors are by-passed and other protocols like
Ethernet can be mapped into SONET/SDH.
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