21.2-S3-C2410X-052003 View Datasheet(PDF) - Samsung

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21.2-S3-C2410X-052003

32-Bit RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 12 USB Host Controller

Overview ................................................................................................................................................ 12-1

USB Host Controller Special Registers ........................................................................................... 12-2

Chapter 13 USB Device

Overview ................................................................................................................................................ 13-1

Feature........................................................................................................................................... 13-1

USB Device Controller Special Registers................................................................................................ 13-3

Function Address Register (FUNC_ADDR_REG)............................................................................ 13-5

Power Management Register (PWR_REG)..................................................................................... 13-6

Interrupt Register (EP_INT_REG/USB_INT_REG) ......................................................................... 13-7

Interrupt Enable Register (EP_INT_EN_REG/USB_INT_REG)....................................................... 13-9

Frame Number Register (FPAME_NUM1_REG/FRAME_NUM2_REG) .......................................... 13-10

Index Register (INDEX_REG)......................................................................................................... 13-11

END Point0 Control Status Register (EP0_CSR) ............................................................................ 13-12

END Point In Control Status Register (IN_CSR1_REG/IN_CSR2_REG)......................................... 13-14

END Point Out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) .............................. 13-16

END Point FIFO Register (EPN_FIFO_REG) ................................................................................. 13-18

MAX Packet Register (MAXP_REG) ............................................................................................... 13-19

END Point Out Write Count Register (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) .............. 13-20

DMA Interface Control Register (EPN_DMA_CON) ........................................................................ 13-21

DMA Unit Counter Register (EPN_DMA_UNIT) .............................................................................. 13-22

DMA FIFO Counter Register (EPN_DMA_FIFO) ............................................................................ 13-23

DMA Total Transfer Counter Register (EPN_DMA_TTC_L,M,H)..................................................... 13-24

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S3C2410X MICROPROCESSOR

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