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S3C4510B View Datasheet(PDF) - Samsung

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S3C4510B Datasheet PDF : 422 Pages
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PROGRAMMER'S MODEL
S3C4510B
M[4:0]
Mode
10000
User
10001
FIQ
10010
IRQ
10011
Supervisor
10111
Abort
11011
Undefined
11111
System
Table 2-1. PSR Mode. Bit Values
Visible THUMB State Registers
R7..R0,
LR, SP
PC, CPSR
R7..R0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
R7..R0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
R7..R0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
R7..R0,
LR_abt, SP_abt,
PC, CPSR, SPSR_abt
R7..R0
LR_und, SP_und,
PC, CPSR, SPSR_und
R7..R0,
LR, SP
PC, CPSR
Visible ARM State Registers
R14..R0,
PC, CPSR
R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq
R12..R0,
R14_irq..R13_irq,
PC, CPSR, SPSR_irq
R12..R0,
R14_svc..R13_svc,
PC, CPSR, SPSR_svc
R12..R0,
R14_abt..R13_abt,
PC, CPSR, SPSR_abt
R12..R0,
R14_und..R13_und,
PC, CPSR
R14..R0,
PC, CPSR
Reserved bits
The remaining bits in the PSRs are reserved. When changing a PSRs flag or
control bits, you must ensure that these unused bits are not altered. Also, your
program should not rely on them containing specific values, since in future
processors they may read as one or zero.
2-10
 

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