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PFM19030 View Datasheet(PDF) - Cree, Inc

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PFM19030 Datasheet PDF : 15 Pages
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PFM19030
Module Application Notes
The PFM19030 was designed to provide a versatile low cost solution for a wide variety of wireless applications
requiring 30 Watt peak output levels. This hybrid module contains two stages of Si LDMOS FET amplification:
a nominally 5 Watt input stage driving a 30 Watt output stage. The module is optimized for efficient, linear operation
with EDGE and CDMA signals. The input and output of this module are partially matched, and require source and load
impedances of nominally 19 and 21 Ohms (much higher than typically required by unmatched Si LDMOS FETs).
These source and load impedances can be achieved with compact conventional external PCB circuitry.
Performance for particular signal protocols can be improved slightly by small adjustments in quiescent currents and
load impedances presented to the module. The data presented in the previous pages was taken at one set of quiescent
currents and in a fixture with source and load impedances that were fixed for all measurements. The data presented is
generally representative of the performance – benefits from further optimization in quiescent current are small.
In addition to the two RF gain stages, there are Sense FET (thermally tracking) devices that serve as optional DC circuit
elements. The Sense FETs are fabricated on the same epi material with nominally identical physical characteristics (but
smaller gate periphery) as the RF devices. The sense devices can be applied as temperature compensation elements in
conjunction with external bias circuitry. Alternatively, the two-stage amplifier can be operated with the Sense FETs
unused (S1 and S2 leads floating).
The base of the module is high conductivity copper of 40 mil thickness. It is well matched to typical PCB material, and
it serves as a heat spreader for the device when mounted as a surface-mount component. The module thermal
characteristics were measured with the unit soldered to a 20 mil thick PCB material with an array of plated via holes for
electrical grounding and thermal sinking. IR scans of this configuration demonstrated maximum die channel
temperatures of 142 degrees C with a PCB base temperature of +95 degrees C, and 10 Watts CW output power.
These modules can be provided in tape-and-reel configuration for high volume applications.
Typical PCB Mounting Pattern
The module outline is indicated by dashed line (0.60 X 1.00 inches). The ground pad is 1.030 X 0.630
inches. Ground vias in this example are 28 mil diameter on 35 mil (or 70 mil) centers. Thermal resistance is
proportional to the thickness of the PC board (height of vias), and inversely proportional to the total ground
hole array periphery (and thickness of plating in the holes). The densely spaced vias in this layout (on 35 mil
spaces) are located in areas of maximum heat generation. The gap between the lead pads and the ground
pad is 25 mils. Note that the underside of the PCB must be connected to a thermal heat sink and ground.
The above hole pattern is an example of one that maximizes thermal transfer. There are numerous
alternative approaches. Depending on the application (signal protocol, thermal environment, etc.), the
number of via holes can be reduced. High average power applications require the most extensive thermal
sinking.
Page 8 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
 

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