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PD3537 View Datasheet(PDF) - OSRAM GmbH

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Description
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PD3537 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Functional Description
The block diagram includes 5 major blocks and internal regis-
ters (indicated by dotted lines).
Display Memory consists of a 5 x 8 bit RAM block. Each of
the four 8-bit words holds 7-bits of ASCII data (bits D0–D6)
and an attribute select bit (Bit D6). The fifth 8-bit memory
word is used as a control word register. A detailed description
of the control register and its functions can be found in the
Control Word section. Each 8-bit word is addressable and can
be read from or written to.
The Control Logic dictates all of the features of the display
device and is discussed in the Control Word section of this
data sheet.
The Character Generator converts the 7-bit ASCII data into
the proper dot pattern for the 128 characters shown in the
character set chart.
The Clock Source can originate either from the internal oscilla-
tor clock or from an external source—usually from the output of
another display in a multiple module array.
The Display Multiplexer controls all display output to the digit
drivers so no additional logic is required for a display system.
The Column Drivers are connected directly to the display.
The Display has four digits. Each of the four digits is com-
prised of 35 LEDs in a 5 x 7 dot array which makes up the
alphanumeric characters.
The intensity of the display can be varied by the Control Word
in steps of 0% (Blank), 25%, 50%, and full brightness.
The Reset pin when activated clears the internal counter. A reset
is usually done after power up and is of very short duration-nano-
seconds or microseconds. If the reset pin is held low for a longer
time (milliseconds) some or all LEDs in the bottom row may light
up. The appearance of lit LEDs during a “reset” is not an indica-
tion of a malfunctioning part. It is advisable to keep the reset
pulse as short as possible to avoid displaying a row of lit LEDs.
Microprocessor Interface
The interface to the microprocessor is through the address
lines. (A0–A2), the data bus (D0–D7), two chip select lines
(CE0, CE1), and read (RD) and write (WR) lines.
The CE0 should be held low when executing a read, or write
operation. CE1 must be held high.
The read and write lines are both active low. During a valid read
the data input lines (D0–D7) become outputs. A valid write will
enable the data as input lines.
Input Buffering
If a cable length of 6 inches or more is used, all inputs to the
display should be buffered with a tri-state non-inverting buffer
mounted as close to the display as conveniently possible. Rec-
ommended buffers are: 74LS245 for the data lines and
74LS244 for the control lines.
Figure 4. Block Diagram
8 Display Memory Control 14
D0-D7
(RAM) 4x8
Reg
1x8
8
4
CE0,CE1 7
A0-A2
RD, WR
Decode
and
Mux
5
Output
Control
Logic
128 Char
ROM
128 x 5
15
1
Output
Latch
1
20
3
CLK SEL
XCLK
RST
OSC
Logic
3
Display
Multiplexer
20
Display
Column
Drivers
3
Row
Drivers
Figure 5. Mode Selection
CEO CE1 RD
WR Operation
0
1
0
0
None
1
X
X
X
None
X
0
X
X
None
X
X
1
1
None
0=Low logic level, 1=High logic level, X=Don’t care
Data Input Commands
CEO CE1 RD WR A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
No Change
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
Read Digit 0 Data to Bus
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
($) Written to Digit 0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
(W) Written to Digit 1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
(f) Written to Digit 2
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
(3) Written to Digit 3
0
1
1
0
1
0
0
1
X
X
X
X
X
X
X
Char. Written to Digit 0
and Cursor Enabled
2001 OSRAM Opto Semiconductors Inc.San Jose, CA
www.inneon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
6
PD2535/6/7, PD3535/6/7, PD4435/6/7
July 5, 2001-14
 

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