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PD3535 View Datasheet(PDF) - OSRAM GmbH

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PD3535 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Electrical and Mechanical Considerations
The CMOS IC of the display is designed to provide resistance
to both Electrostatic Discharge Damage and Latch Up due to
voltage or current surges. Several precautions are strongly rec-
ommended to avoid overstressing these built-in safeguards.
ESD Protection
Display users should be careful to handle the devices consis-
tent with Standard ESD protection procedures. Operators
should wear appropriate wrist, ankle or feet ground straps and
avoid clothing that collects static charges. Work surfaces, tools
and transport carriers that come into contact with unshielded
devices or assemblies should also be appropriately grounded.
Latch up Protection
Latch up is a condition that occurs in CMOS ICs after the input
protection diodes have been broken down. These diodes can
be reversed through several means:
VIN<GND, VIN>VCC + 0.5 V, or through excessive currents
forced on the inputs. When these situations exist, the IC may
develop the response of an SCR and begin conducting as much
as one amp through the VCC pin. This destructive condition will
persist (latched) until device failure or the device is turned off.
The Voltage Transient Suppression Techniques and buffer inter-
faces for longer cable runs help considerably to prevent latch
conditions from occurring. Additionally, the following Power Up
and Power Down sequence should be observed.
Power up Sequence
1. Float all active signals by tri-stating inputs to displays.
2. Apply VCC and GND to the display.
3. Apply active signals to the displays by enabling all input
signals per application.
Power Down Sequence
1. Float all active signals by tri-stating the inputs to the display.
2. Turn off the power to the display.
Soldering Considerations
These displays can be hand soldered with SN63 solder using a
grounded iron set to 260°C.
Wave soldering is also possible following these conditions: Pre-
heat that does not exceed 93°C on the solder side of the PC
board or a package surface temperature of 85°C. Water soluble
organic acid ux (except carboxylic acid) or rosin-based RMA
ux without alcohol can be used.
Wave temperature is 245°C ±5°C with a dwell between 1.5
seconds to 3.0 seconds. Exposure to the wave should not
exceed temperatures above 260°C, for 5 seconds at 0.063"
below the seating plane. The packages should not be
immersed in the wave.
Voltage Transient Suppression
It has become common practice to provide 0.01 µF bypass
capacitors liberally in digital systems. Like other CMOS cir-
cuitry, the Intelligent Display controller chip has very low
power consumption and the usual 0.01 µF would be adequate
were it not for the LEDs. To prevent power supply transients,
capacitors with low inductance and high capacitance at high
frequencies are required. This suggests a solid tantalum or
ceramic disc for high frequency bypass. For multiple display
module systems distribute the bypass capacitors evenly, keep-
ing capacitors as close to the power pins as possible. Use a
0.01 µF capacitor for each display module and a 22 µF for
every third display module.
Figure 7. Character Set
D0 0
10
1
0
1
01
0
1
0
1
0
1
0
1
ASCII D1 0
01
1
0
0
11
0
0
1
1
0
0
1
1
CODE D2 0
00
0
1
1
11
0
0
0
0
1
1
1
1
D3 0
00
0
0
0
00
1
1
1
1
1
1
1
1
D6 D5 D4 HEX 0
1
2
3
4
5
6
7
8
9A
BC
DE
F
000 0
Notes:
1. A2 must be held high for ASCII data.
2. Bit D7=1 enables attributes for the
assigned digit.
001 1
010 2
011 3
100 4
101 5
110 6
111 7
2001 OSRAM Opto Semiconductors Inc.San Jose, CA
www.inneon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
10
PD2535/6/7, PD3535/6/7, PD4435/6/7
July 5, 2001-14
 

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