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NE5550979A-T1 View Datasheet(PDF) - Renesas Electronics

Part NameDescriptionManufacturer
NE5550979A-T1 Silicon Power LDMOS FET Renesas
Renesas Electronics Renesas
NE5550979A-T1 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
NE5550979A
COMPONENT LAYOUT OF TEST CIRCUIT FOR 157 MHz
VGS
GND
VDS
C1
L11
C12
C10
C11
R1
C1
L1 C20
C21 L20
C22
C23 C24
TYPICAL CHARACTERISTICS 2 (TA = 25°C)
R: f = 157 MHz, VDS = 3.6/4.5/6/7.5/9 V, IDset = 200 mA, Pin = 0 to 27 dBm
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
45
Pout - 3.6 V
4.5
Pout - 4.5 V
Pout - 6.0 V
40 Pout - 7.5 V
4.0
Pout - 9 V
35
3.5
30
3.0
POWER GAIN, POWER ADDED
EFFICIENCY vs. INPUT POWER
40
80
Gp - 3.6 V
Gp - 4.5 V
Gp - 6 V
35
Gp - 7.5 V
70
Gp - 9 V
ηadd - 3.6 V
ηadd - 4.5 V
30
ηadd - 6 V
60
ηadd - 7.5 V
ηadd - 9 V
25
50
25
2.5
20
40
20
IDS - 3.6 V
2.0
IDS - 4.5 V
IDS - 6 V
15
30
15 IDS - 7.5 V
1.5
IDS - 9 V
10
20
10
1.0
5
0.5
5
10
0
–5 0
0.0
5 10 15 20 25 30
Input Power Pin (dBm)
0
–5 0
0
5 10 15 20 25 30
Input Power Pin (dBm)
R09DS0031EJ0300 Rev.3.00
Mar 12, 2013
Page 6 of 11
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