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MTV312MS64 View Datasheet(PDF) - Unspecified

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MTV312MS64 Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV312M64
(Rev 0.99)
VSYNC
HSYNC
Digital Filter
Present
Check
Vpre
Polarity Check &
Freq. Count
Vfreq
Vpol
Vbpl
CVSYNC
XOR
Vself
Present
Check
CVpre
XOR VBLANK
Digital Filter
Polarity Check &
Sync Seperator
Hpol
Present Check &
Freq. Count
Hpre
Hfreq
Composite
Pulse Insert
XOR
Hself
H/V SYNC Processor Block Diagram
Hbpl
XOR HBLANK
6.1 Composite SYNC separation/insertion
The MTV312M continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC then has 8us delay compared to the original signal.
The MTV312M can also insert pulse to HBLANK output during composite VSYNC’s active time. The width of
insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert pulse
of HBLANK can be disabled or enabled by setting “NoHins” control bit.
6.2 H/V Frequency Counter
MTV312M can discriminate HSYNC/VSYNC frequency and save the information in XFRs. The 14-bit
Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The
output value is then [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12-bit
Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch.
The output value is then (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflows. Table 6.2.1 and Table 6.2.2 show the HCNT/VCNT value under the operations of
12MHz.
Revision 0.99
- 10 -
2001/07/26
 

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