ISB35083 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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ISB35083

HCMOS STRUCTURED ARRAY

STMicroelectronics 

ISB35000 SERIES

Table 5. Module Generator Library

Cell

Description

SPRAM

Metallised

8K bits max

2048 word max 64 bit max

Zero static current

Tristate output

Embedded

256K bits max

16K word max 64 bit max

Zero static current

Tristate outputs

DPRAM

Metallised

4K bits max

1024 word max 64 bit max

Zero static current

Separate read/write ports

Tristate outputs

Embedded

128K bits max

8K word max 64 bit max

Zero static current

Tristate outputs

ROM

Embedded

2M bits max

32K word max 64 bit max

Diffusion programmable

Tristate outputs

These allow access to technologies that have been hitherto the domain of standard products.

Examples include mixed mode cells for graphics,

DAC/ADC’s (4-9 bit), PLL applications, and Digital

Signal Processor functions for cellular comms, fax

and high-speed modem.which initially consist of a

Triple 8-bit DAC, Graphics RAM, Clock Multiplier

PLL and Frequency Synthesis PLL.

100 Mbps serial transputer links coupled with large

and fast memory can be used for pipelining, cach-

ing and synchro circuits in modern RISC computing

architectures.

Viterbi and Reed Solomon cores aim at the HDTV

and satellite transmission markets. To support tele-

com needs for CCITT standard applications,

ADPCM cells supporting CT2 protocol have been

developed.

DESIGN FOR TESTABILITY

The time and cost for ASIC testing increases expo-

nentially as the complexity and size of the ASIC

grows. Using a design for testability methodology

allows large, more complex ASICs to be efficiently

and economically tested.

ISB35000 supports the JTAG boundary Scan and

both edge and level sensitive scan design tech-

niques by providing the necessary macrocells.

Scan testing aids device testability by permitting

access to internal nodes without requiring a sepa-

rate external connection for each node accessed.

Testability is assured at device level with the close

coupling of LSSD latch elements, Automatic Test

Pattern Generation (ATPG) and high pattern depth

tester architecture.

At system level, SGS-THOMSON fully supports

IEEE 1149.1, within the I/O structure utilised in this

family. Several types of core scan cells are provided

in the ISB35000 Series library. Examples include

FDxS/FJKxS cells which are edge sensitive and

LSxx cells which are true LSSD cells.

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