ISB35000SERIES View Datasheet(PDF) - STMicroelectronics

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ISB35000SERIES

HCMOS STRUCTURED ARRAY

STMicroelectronics 

ISB35000 SERIES

TECHNOLOGY OVERVIEW

The design of ISB35000 internal cell is a proprietary

design variation of the CONTINUOUS ARRAY ar-

chitecture previously used in ISB12000, 18000,

and 24000 array families. This proprietary (patent

pending) configuration has been named THE DOU-

BLE BUFFER CELL. This configuration provides a

core that is completely filled with potently active

transistors. Surrounding the core are configura-

tional specialized transistors forming a Sea of I/O

giving a high degree of flexibility to the system

designer. The ISB35000 supports the routing of

signals over unused transistors as needed. Three

levels of metal are utilized, intracell and intercell

wiring are limited to first metal with second and third

metal levels dedicated to interconnect wiring and

power distribution.

The basic cell is made up of four N and four P type

transistors that are vertically arranged. The centre

two pairs of transistor have common polysilicon

Figure 2. Internal Core Cell

10 µm

30 µm

ISB35_PA

gates, while the outer two pairs have separate

gates for the polysilicon transistors. The cell was

configured to allow extremely high density macro

design for internal macro cell counts over one

million gates while enabling paralleling of transis-

tors to allow high drive capability and the symmetry

of the rise and fall of macro outputs hence the

DOUBLE BUFFER name. Each cell has twelve

horizontal wiring channels on first metal, four verti-

cal wiring channels on second metal and a further

twelve channels on third metal. The HCMOS5 proc-

ess technology allows for adjacent vias and

stacked via1, via2 with or without silicon contacts.

The transistor width utilized by the DOUBLE BUFF-

ER cell is very small as compared to previous

technologies. Even though the basic cell consists

of eight transistors adjacent macros share transis-

tors across the cell borders allowing high density

usage of the resources.

Macros are constructed using resources from one

half cell to tens of cells dependent upon the com-

plexity of the function. The transistors within and

between cells are placed adjacent to each other

sharing source and drain regions. All isolation is

achieved by cutting off adjacent source drain re-

gions with turned off transistors.

A further feature of the Double Buffer cell that helps

allow it to obtain very high density usage is the

proprietary (patent pending) method of localized

power distribution. A major feature of the HCMOS5

process is salicided active areas. This results in

source drain areas that are of one to two ohms

resistance as opposed to the hundreds or thou-

sands of ohms of source drain resistance in pre-

vious technologies. This very low resistance is one

reason that very low transistor widths could be

utilized in the cell design since drive is not lost due

to source drain resistance. This use of low width

transistors results in lower capacitance loading of

the gates due to the smaller areas utilized. Low

resistance, low capacitance, and small gates re-

sults in low power usage for inverters as compared

to previous ISB technologies. This reduction in

power allows the use of salicided active stripes for

power distribution replacing the first level metal

buses used in previous technologies. This removal

of the metal one power buses simplified macro

layout allowing additional wiring resources to be left

for the router allowing a higher density usage of the

array than would be achievable with previous

power distribution techniques. One other gain in the

performance of the array and its usability for the

customer was derived from the use of the salicided

3/15

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