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ISB35832 HCMOS STRUCTURED ARRAY ST-Microelectronics
STMicroelectronics ST-Microelectronics
ISB35832 Datasheet PDF : 15 Pages
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ISB35000 SERIES
GENERAL DESCRIPTION
The ISB35000 array series uses a high perform-
ance, low voltage, triple level metal, HCMOS 0.5
micron process to achieve sub-nanosecond inter-
nal speeds while offering very low power dissipation
and high noise immunity. The potential total gate
count ranges above 1 million equivalent usable
gates. The array operates over a Vdd voltage range
of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over
600 signals and 1000 pins dependent upon the
package technology utilized. A Sea of I/O approach
has been followed to give a solution to today’s
problems of drive levels and specialized interface
standards. The array does not utilize a set bond pad
spacing but allows for pad spacings from 80 mi-
crons upwards.
The I/O can be configured for circuits ranging from
low voltage CMOS and TTL to 200 mHz plus low
swing differential circuits. Standards like GTL,
SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0
Volt interfaces are currently being addressed. A
specialized set of impedance matched transmis-
sion line driver LVTTL type circuits are also avail-
able with 25, 35, 45, and 55 Ohm output
impedance. These buffers sacrifice direct current
capabilities for matching positive and negative volt-
age and current waveforms.
Figure 1. Advantages of stacked contacts and vias
CONVENTIONAL VIA LAYOUT
STACKED VIA LAYOUT
1st
VIA
CONTACT
GATE
2nd
VIA
METAL 3
METAL 2
3rd DIELECTRIC
METAL 1
2nd DIELECTRIC
1st DIELECTRIC
ISOLATION
SUBSTRATE
CONTACT/VIA
PLUGS
- STACKABLE CONTACTS + VIAs ALLOW MUCH HIGHER DENSITY (AREA SAVINGS UP TO 20% FOR R.L.)
- SIMPLIFIED ROUTING AND DESIGN RULE CHECKING
ISB35_VA
2/15
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