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ISB35832 View Datasheet(PDF) - STMicroelectronics

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Description
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ISB35832
ST-Microelectronics
STMicroelectronics ST-Microelectronics
ISB35832 Datasheet PDF : 15 Pages
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ISB35000 SERIES
HCMOS STRUCTURED ARRAY
FEATURES
0.5 micron triple layer metal HCMOS process
featuring retrograde well technology, low
resistance salicided active areas, polysilicide
gates and thin metal oxide.
3.3 V optimized transistor with 5 V I/O interface
capability
2 - input NAND delay of 0.210 ns (typ) with
fanout = 2.
Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48 mA
with slew rate control, current spike suppression
and impedance matching.
Metallised generators to support SPRAM and
DPRAM, plus an extensive embedded function
library.
Combines Standard Cell Features with Sea of
Gates time to market.
PRELIMINARY DATA
Fully independent power and ground
configurations for inputs, core and outputs.
Programmable I/O ring capability up to 1000
pads.
Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
Active pull up and pull down devices.
Buskeeper I/O functions.
Oscillators for wide frequency spectrum.
Broad range of 400 SSI cells.
300 element macrofunction library.
Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary Scan
architecture built in.
Cadence and Mentor based design system with
interfaces from multiple workstations.
Broad ceramic and plastic package range.
Latchup trigger current +/- 500 mA.
ESD protection +/- 4000 volts.
Table 1. Product range
Internal
Device Name
Total Sites1
Estimated 2
Gates
Total Usable3
Gates
Maximum4
Device Pads
Maximum5
I/O
ISB35083
124,416
82,944
58,060
188
172
ISB35130
194,400
129,600
90,720
232
216
ISB35166
249,696
166,464
116,524
260
244
ISB35208
311,904
207,936
145,555
288
272
ISB35279
418,176
278,784
195,148
332
316
ISB35389
584,064
389,376
253,094
388
372
ISB35484
726,624
484,416
314,870
432
416
ISB35666
998,784
665,856
399,513
504
488
ISB35832
1,247,616
831,744
499,046
560
544
Notes : 1. Internal sites is based on the number of placement sites available to the route and place software
2. A factor of 1.5 is used to derive the gate complexity from the total available sites. This number is in Nand2 equivalents
3. Factors of 70%, 65%, and 60% have been used to calculate the routing efficiency. This number may vary depending on the
design.
4. 16 corner pads are dedicated to internal and external power supplies. I/O pads may be configured for additional power.
5. Maximum I/O = total device pads minus power pads.
May 1994
1/15
 

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