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ISB35484 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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ISB35484
ST-Microelectronics
STMicroelectronics ST-Microelectronics
ISB35484 Datasheet PDF : 15 Pages
First Prev 11 12 13 14 15
ISB35000 SERIES
DESIGN ENVIRONMENT
Several interface levels are possible between SGS-
THOMSON and the customer in the undertaking of
an ASIC design. The four levels of interface are
shown in Figure 7. Level 1 is characterized by
SGS-THOMSON receiving the system specification
and taking the design through to validation and
fabrication. At level 2 interface the designer sup-
plies a complete logic design implemented in a
standard generic logic family. SGS-THOMSON
then takes the design through to layout, validation
and fabrication.
Level 3 is the most common and preferred interface
level. Logic capture and pre-layout simulation are
performed by the designer using an SGS-THOM-
SON supported design kit. The design is then taken
through layout, validation and fabrication by SGS-
THOMSON.
The SGS-THOMSON design system validates all
designs before fabrication. Design kits areprovided
that allow schematic capture entry via Mentor
Graphics and Cadence Amadeus. Simulation is
supported on Cadence Amadeus and Mentor
Graphics. Full support is also provided for Cadence
Verilog, Synopsys VSS and System Hilo simula-
tors. Figure 8 shows the SGS-THOMSON Design
Flow.
Figure 7. Customer/SGS-THOMSON Interface Levels
SYSTEM
SYSTEM
SPECIFICATION
LOGIC
DESIGN
SCHEMATIC
CAPTURE
DESIGN
VERIFICATION
PRE-LAYOUT
SIMULATION
LAYOUT
POST-LAYOUT
SIMULATION
MANUFACTURE
AND TEST
CUSTOMER
LEVEL 1
LEVEL 2
CUSTOMER
LEVEL 3
LEVEL 4
CUSTOMER
CUSTOMER
ISB35_VC
11/15
 

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