1Semiconductor
FEDL2201-01
ML2201–XXX
TIMING DIAGRAMS
Timing Diagram at Powering On
VDD
PDWN
ST
PI
tRST
tPDH
Reset
Power Down
NOTE: The LSI’s reset operation can be performed by using a level input combination of PDWN = “L”,
ST = “L” and PI = “H”. After powering on, the initial reset operation is required at the above timing.
Timing Diagram at Powering Up and Standby State
PDWN
AOUT
1/2 IAOUT
tDAR
tDAF
Timing Diagram for Playback
PDWN
ST
PI
AOUT
tPDSS
......
tSPS
tPW
tPC
tSPH
tSAS
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