MC74AC573N View Datasheet(PDF) - ON Semiconductor
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MC74AC573N Datasheet PDF : 12 Pages
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MC74AC573, MC74ACT573
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
L
H
H
H
L
H
L
L
L
L
H
X
X
O0
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW−to−HIGH Transition of Clock
D0
D1
D2
D3
Functional Description
The MC74AC573/74ACT574 contains eight D−type
latches with 3−state output buffers. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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