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MAX1544 View Datasheet(PDF) - Maxim Integrated

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MAX1544 Datasheet PDF : 42 Pages
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Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Table 1. Component Selection for Standard Multiphase Applications
DESIGNATION
Input Voltage Range
VID Output Voltage
(D4D0)
Suspend Voltage
(SUS, S0S1)
Maximum Load Current
Number of Phases (ηTOTAL)
Inductor (per Phase)
Switching Frequency
High-Side MOSFET
(NH, per phase)
Low-Side MOSFET
(NL, per phase)
Total Input Capacitance (CIN)
MAX1544
AMD MOBILE COMPONENTS
Circuit of Figure 1
7V to 24V
1.5V
(D4D0 = 00010)
Not used
(SUS = GND)
60A
Two phases
(1) MAX1544
0.6µH Panasonic ETQP1H0R6BFA
300kHz (TON = REF)
Siliconix (1) Si7886DP or
International Rectifier (2) IRF6604
Siliconix (2) Si7442DP or
International Rectifier (2) IRF6603
(8) 10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
MAX1544
AMD DESKTOP COMPONENTS
Circuit of Figure 12
7V to 24V
1.5V
(D4D0 = 00010)
Not used
(SUS = GND)
70A
Four phases
(1) MAX1544 + (2) MAX1980
0.7µH Panasonic ETQP2H0R7BFA
or 0.8µH Sumida CDEP105L-0R8
300kHz (TON = REF)
International Rectifier (1) IRF7811W
or Fairchild (1) FDS6694
Fairchild (2) FDS6688 or Siliconix (1) Si7442DP
(8) 10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
Total Output Capacitance
(COUT)
Current-Sense Resistor
(RSENSE, per Phase)
(4) 680µF, 2.5V
Sanyo 2R5TPD680M
1m
Panasonic ERJM1WTJ1M0U
(5) 680µF, 2.5V
Sanyo 2R5TPD680M
1m
Panasonic ERJM1WTJ1M0U
After the phase-overlap mode ends, the controller auto-
matically begins with the opposite phase. For example,
if the secondary phase provided the last on-time pulse
before overlap operation began, the controller starts
switching with the main phase when overlap operation
ends.
Power-Up Sequence
The MAX1544 is enabled when SHDN is driven high
(Figure 2). The reference powers up first. Once the ref-
erence exceeds its UVLO threshold, the PWM controller
evaluates the DAC target and starts switching.
For the MAX1544, the slew-rate controller ramps up the
output voltage in 25mV increments to the proper operat-
ing voltage (see Tables 3 and 4) set by either D0D4
(SUS = GND) or S0S1 (SUS = REF or high). The ramp
rate is set with the RTIME resistor (see the Output Voltage
Transition Timing section).
The ramp rate is set with the RTIME resistor (see the
Output Voltage Transition Timing section). The con-
troller pulls VROK low until at least 3ms after the
MAX1544 reaches the target DAC code.
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