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MAX1007CAG View Datasheet(PDF) - Maxim Integrated

Part Name
Description
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MAX1007CAG
MaximIC
Maxim Integrated MaximIC
MAX1007CAG Datasheet PDF : 12 Pages
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Mobile-Radio Analog Controller
Pin Description
PIN
NAME
FUNCTION
1
RPS
Used to measure reverse-transmit power level. Only active in transmit mode when PKWDW = 1,
SDAC[F/R] = Reverse. When not selected, this pin is internally pulled to AGND through a 200switch.
Used to measure forward power-sense class 2/3/4. Only active in transmit mode when GDAC[Power
2
FPS2
Class] = Class 2/3/4, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally
pulled to AGND through a 200switch.
Used to measure forward power-sense level 1. Only active in transmit mode when GDAC[Power Class] =
3
FPS1
Class 1, PKWDW = 1, and SDAC[F/R] = Forward. When not selected, this pin is internally pulled to AGND
through a 200switch.
4
SDAC
Buffered output of 7-bit DAC. Controls gain stage in up/down converter.
5
AVDD
Analog Supply Voltage
6
XDAC
Unbuffered output of 6-bit DAC. Used to control VCXO frequency.
7
AGND
Analog Ground
8
REF
1.028V Reference Voltage Output
9
KDAC
Buffered output of 7-bit DAC. Controls gain stage in external modulator block.
10
GDAC
Buffered output of 6-bit DAC. Controls negative gate bias voltage of external power amplifier.
11
SDG
Software-Programmable Logic Output. Can be used to shut down external bias generator.
Best-Antenna Digital Output. Result of preamble-switched diversity measurement (Figure 2). “0” indicates
12
BANT
more power was sensed from period A with respect to period B. “1” means vice versa. Period A is
sensed in the first 12 clock periods following the PSDWDW rising edge.
13
PSDCTRL
Preamble-Switched Diversity Measurement-Control Signal (Figure 2). This pin has a 20kpull-down
resistor to digital ground.
14
PSDWDW
Preamble-Switched Diversity Measurement Window (Figure 2). This pin has a 20kpull-down resistor to
digital ground.
15 ADCCTRL RSSI/Power-Sense Measurement-Control Input (Figure 1)
16
PKWDW RSSI/Power-Sense Measurement-Window Digital Input (Figure 1)
17
DOUT
Serial-Data Output. Enabled when CS is low.
18
DGND
Digital Ground
19
SCLK
Serial-Clock Input. Clock can be stopped and resumed at any time (40% to 60% duty cycle).
20
DVDD
Digital Supply Voltage
21
DIN
Serial-Data Input
22
CS
Chip Select Input. Enables serial interface when low.
23
PSBIAS Power-Sense Measurement Buffered-Bias Output Voltage. Active only during power sensing.
Received-Signal Strength Indicator Analog Input for power-sense and antenna diversity measurements.
24
RSSI
Signal goes into peak-detector circuit and is sampled at the end of the measurement window by the 8-bit
ADC. Only active in receive mode when PKWDW = 1. Peak-detector circuit can be bypassed by using
CH1 as the ADC input.
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