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KM416V254D View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM416V254D 256K x 16Bit CMOS Dynamic RAM with Extended Data Out Samsung
Samsung Samsung
KM416V254D Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
KM416C254D, KM416V254D
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 50pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCDtRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled
write cycle and read-modify-write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. tASC6ns, Assume tT = 2.0ns
12. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS going.
KM416C/V254D/DL Truth Table
RAS
LCAS
UCAS
W
H
H
H
H
L
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
H
OE
DQ0 - DQ7
H
Hi-Z
H
Hi-Z
L
DQ-OUT
L
Hi-Z
L
DQ-OUT
H
DQ-IN
H
-
H
DQ-IN
H
Hi-Z
DQ8-DQ15
Hi-Z
Hi-Z
Hi-Z
DQ-OUT
DQ-OUT
-
DQ-IN
DQ-IN
Hi-Z
STATE
Standby
Refresh
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-
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