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H27UAG8T2B View Datasheet(PDF) - Hynix Semiconductor

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Description
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H27UAG8T2B
Hynix
Hynix Semiconductor Hynix
H27UAG8T2B Datasheet PDF : 61 Pages
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Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
4.10. Multi Plane Cache Program (available only within a block)
The device supports multi plane cache program, which enables high program throughput by programming two pages.
The serial data-loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data for the first page. Address for this page must be within first plane (A<22>=0). The
data of first page other than those to be programmed do not need to be loaded. The device supports random data
input exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data
input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be
issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within second
plane (A<22>=1). The data of second page other than those to be programmed do not need to be loaded. Cache
Program Confirm command (15h) makes parallel programming of both pages start. And last page inputs Program
confirm command (10h). the last page of the target programming sequence must be programmed with actual Page
Program command (10h). If the operation is terminated, Issue FFh reset before next operation. If multiplane
cache program begins, multiplane sequence should be used until multiplane cache program is ended.
Figure 44 shows the command sequence for Multi Plane Cache Program operation. After the "15h"or"10h"
command, the result per plane of the operation is shown through the "78h" Multi Plane Read Status command.
Figure 44. Multi plane cache program
I/Ox
Column address : Valid
Page address : Page M
Plane address : Fixed ‘Low’
Block address : block J
Address
Data
80h
(5 Cycle)
Input
11h
R/B#
A
I/Ox
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘Low’
Block address : block J
Address
Data
80h
(5 Cycle)
Input
11h
R/B#
tDBSY
tDBSY
Column address : Valid
Page address : Page M
Plane address : Fixed ‘High’
Block address : block K
Address
Data
81h
(5 Cycle)
Input
15h
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘High’
Block address : block K
81h
Address
(5 Cycle)
Data
Input
10h
A
tCBSYW
78h
tPROG
Address
(3 Cycle)
Status
per plane
Notes:
1.
2.
3.
4.
5.
6.
7.
Plane 0 and Plane 1 should be selected within the same chip
Only one block should be selected from the each Plane.
Multi Plane cache program is available only within a block per Plane.
Selected Page address except for A22 within two blocks must be same.
The operation has to be terminated with “10h” command.”
Any command between 11h and 81h is prohibited except 70h/78h and FFh.
Read Status command can be 70h or 78h. Reading the Status per Plane is available only 78h.
4.11. Copy-Back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page
without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated
and the rest of the block needs to be copied to the newly assigned free block. Copy-Back operation is a sequential exe-
cution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with
"35h" command and the address of the source page moves the whole 8,640-byte data into the internal data buffer. A
bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need
to be reloaded. Therefore, Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h)
Rev 1.0 / Aug. 2010
46
 

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