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H27UAG8T2B View Datasheet(PDF) - Hynix Semiconductor

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Description
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H27UAG8T2B
Hynix
Hynix Semiconductor Hynix
H27UAG8T2B Datasheet PDF : 61 Pages
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Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
Note:
Data Input cycle is accepted to data register on the rising edge of WE#, when CLE and CE# and ALE are low,
and device is not Busy state.
3.4. Data Output Cycle Timings (CLE=L, WE#=H, ALE=L, WP#=H)
Figure 9. Data output cycle timings
CE#
RE#
tREA
tRC
t REH
tREA
tRHZ
I/Ox
Dout
t RR
Dout
tCHZ
tREA
tRHZ
tRHOH
Dout
R/B#
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( tCHZ, tRHZ)
2. tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
3.5. Data Output Cycle Timings (EDO type, CLE=L, WE#=H, ALE=L)
Figure 10. Data output cycle timings (EDO)
CE#
RE#
I/Ox
R/B#
tRC
tRP
tREH
tREA
tCR
tRR
tREA
tRLOH
Dout
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( tCHZ, tRHZ)
Rev 1.0 / Aug. 2010
tCHZ
tRHZ
tRHOH
Dout
: Don’t care
24
 

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