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H27UAG8T2B View Datasheet(PDF) - Hynix Semiconductor

Part Name
Description
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H27UAG8T2B
Hynix
Hynix Semiconductor Hynix
H27UAG8T2B Datasheet PDF : 61 Pages
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Release
H27UAG8T2B Series
16Gb (2048M x 8bit) NAND Flash
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi Plane page read, Multi Plane cache read, and Multi Plane read for copy-back must be used after Multi Plane
programmed page, Multi Plane cache program, and Multi Plane copy-back program.
1.8. Mode Selection
CLE
ALE
CE#
WE#
RE#
WP#
MODE
H
L
L
L
H
L
H
X
Command Input
Read Mode
H
X
Address Input ( 5 Cycles )
H
L
L
L
H1)
L
H
H
Command Input
Write Mode
H
H
Address Input ( 5 Cycles )
L
L
L
H
H
Data Input
L
L1)
L
H
X
Sequential Read and Data Output
X
X
X
H3)
H3)
X
X
X1)
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
L
X
X
H
X
X
0V/Vcc2)
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
Stand-By
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to
avert unintended data out. In this time, only Reset, Read Status, and Multi Plane Read Status can be inputted to
the device.
Rev 1.0 / Aug. 2010
11
 

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