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KM44H16030AT-FZ View Datasheet(PDF) - Samsung

Part NameDescriptionManufacturer
KM44H16030AT-FZ 128Mb DDR SDRAM Samsung
Samsung Samsung
KM44H16030AT-FZ Datasheet PDF : 49 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
128Mb DDR SDRAM
1. Key Features
1.1 Features
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Target
1.2 Operating Frequencies
Speed
DLL jitter
*CL : Cas Latency
Maximum Operation
Frequency
PC266A(-Z)
PC266B(-Y)
133MHz@CL2 133MHz@CL2.5
±0.75ns
±0.75ns
PC200(-0)
100MHz@CL2
±0.8ns
Table 1. Operating frequency and DLL jitter
1.3 Device information by Organization
Density
128Mb
Part No.
KM44L32031BT-G(F)Z/Y/0
KM48L16031BT-G(F)Z/Y/0
KM416L8031BT-G(F)Z/Y/0
Operating Freq.
133/133/100MHz
Interface Package
SSTL_2
66pin
TSOP II
- 9 of 63 -
REV. 0.61 August 9. '99
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