KM44H16040T-FY View Datasheet(PDF) - Samsung
Part Name
Description
View to exact match
KM44H16040T-FY Datasheet PDF : 49 Pages
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128Mb DDR SDRAM
Target
Parameter
Symbol
PC266A
Min Max
PC266B
Min Max
PC200
Min Max
Unit
Note
Exit self refresh to bank active command
tXSA
75
75
80
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
64Mb, 128Mb
256Mb
tREF
15.6
7.8
15.6
15.6
7.8
7.8
us
1
us
1
Output DQS valid window
tDV
0.35
0.35
0.35
tCK
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
4
Auto precharge write recovery + Precharge time tDAL
35
35
35
ns
.
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
Table 14. AC timing parameters and specifications
- 43 of 63 -
REV. 0.61 August 9. '99
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