KM44H16030C-GZ View Datasheet(PDF) - Samsung
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Description
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KM44H16030C-GZ Datasheet PDF : 49 Pages
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128Mb DDR SDRAM
Target
8.2 AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Last data in to Write command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tCDLR
tCDLW
tCCD
tCK
tCH
Clock low level width
tCL
DQS-out access time from CK/CK
tDQSCK
Output data access time from CK/CK
tAC
Data strobe edge to ouput data edge
tDQSQ
Read Preamble
tRPRE
Read Postamble
tRPST
Data out high impedence time from CK/CK tHZQ
CK to valid DQS-in
tDQSS
DQS-in setup time
tWPRES
DQS-in hold time
tWPREH
DQS-in high level width
tDQSH
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tDQSL
tDSC
tIS
tIH
tMRD
tDS
tDH
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
tDIPW
tPDEX
tXSW
- Z(PC266@CL=2)
Min
Max
65
75
45
12K
20
20
15
2
1
0
1
7.5
15
7
15
0.45
0.55
0.45
-0.75
-0.75
-0.5
0.9
0.4
-0.75
0.75
0
0.25
0.4
0.55
+0.75
+0.75
+0.5
1.1
0.6
+0.75
1.25
0.6
0.4
0.6
0.9
1.1
1.1
1.1
15
0.5
0.5
1.75
10
95
- Y(PC266@CL=2.5) - 0(PC200@CL=2)
Unit Note
Min
Max
Min
Max
65
70
ns
75
80
ns
48
12K
48
12K
ns
20
20
ns
20
20
ns
15
15
ns
2
2
tCK
1
1
tCK
0
0
tCK
1
1
tCK
10
15
10
15
ns
7.5
15
8
15
ns
0.45
0.55
0.45
0.55 tCK
0.45
0.55
0.45
0.55 tCK
-0.75
+0.75
-0.8
+0.8
ns
-0.75
+0.75
-0.8
+0.8
ns
-0.5
+0.5
-0.6
+0.6
ns
0.9
1.1
0.9
1.1
tCK
0.4
0.6
0.4
0.6
tCK
-0.75
+0.75
-0.8
+0.8
ns
2
0.75
1.25
0.75
1.25 tCK
0
0
ns
3
0.25
0.25
tCK
0.4
0.6
0.4
0.6
tCK
0.4
0.6
0.4
0.6
tCK
0.9
1.1
0.9
1.1
tCK
1.1
1.2
ns
1.1
1.2
ns
15
16
ns
0.5
0.6
ns
0.5
0.6
ns
1.75
2
ns
10
10
ns
116
ns
- 42 of 63 -
REV. 0.61 August 9. '99
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