datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

KM44H16041AC-GY View Datasheet(PDF) - Samsung

Part Name
Description
View to exact match
KM44H16041AC-GY
Samsung
Samsung Samsung
KM44H16041AC-GY Datasheet PDF : 49 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
128Mb DDR SDRAM
Target
3.3.13 Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris-
ing edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh com-
mand is applied. No control of the external address pins is required once this cycle has started because of the
internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the auto refresh command and the next activate command or subsequent auto refresh command
must be greater than or equal to the tRFC(min).
CK
CK
Command
PRE
Auto
Refresh
CKE = High
tRP
tRFC
CMD
Self Refresh
Figure 21. Auto refresh timing
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in
self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally
disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE
high for longer than tXSR for locking of DLL.
CK
CK
Command
CKE
Self
Refresh
Active
Read
tXSA
tXSR
Figure 22. Self refresh timing
- 31 of 63 -
REV. 0.61 August 9. '99
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]