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CAT28F512G-12T View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part NameCAT28F512G-12T Catalyst
Catalyst Semiconductor => Onsemi Catalyst
Description512K-Bit CMOS Flash Memory
CAT28F512G-12T Datasheet PDF : 15 Pages
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CAT28F512
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified.
Symbol
ILI
Parameter
Input Leakage Current
Limits
Min.
Max.
Unit
±1
µA
ILO
Output Leakage Current
±1
µA
ISB1
VCC Standby Current CMOS
100
µA
ISB2
VCC Standby Current TTL
ICC1
VCC Active Read Current
1
mA
30
mA
ICC2(1) VCC Programming Current
15
mA
ICC3(1) VCC Erase Current
15
mA
ICC4(1) VCC Prog./Erase Verify Current
15
mA
IPPS
IPP1
IPP2(1)
VPP Standby Current
VPP Read Current
VPP Programming Current
±10
µA
200
µA
30
mA
IPP3(1) VPP Erase Current
30
mA
IPP4(1) VPP Prog./Erase Verify Current
5
mA
VIL
Input Low Level TTL
–0.5
0.8
V
VILC
Input Low Level CMOS
–0.5
0.8
V
VOL
Output Low Level
0.45
V
VIH
Input High Level TTL
2
VCC+0.5
V
VIHC
Input High Level CMOS
VCC*0.7 VCC+0.5
V
VOH1 Output High Level TTL
2.4
V
VOH2 Output High Level CMOS
VCC–0.4
V
VID
A9 Signature Voltage
11.4
13
V
IID(1)
A9 Signature Current
200
µA
VLO
VCC Erase/Prog. Lockout Voltage
2.5
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Test Conditions
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
CE = VCC ±0.5V,
VCC = 5.5V
CE = VIH, VCC = 5.5V
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
VCC = 5.5V,
Programming in Progress
VCC = 5.5V,
Erasure in Progress
VCC = 5.5V, Program or
Erase Verify in Progress
VPP = VPPL
VPP = VPPH
VPP = VPPH,
Programming in Progress
VPP = VPPH,
Erasure in Progress
VPP = VPPH, Program or
Erase Verify in Progress
IOL = 5.8mA, VCC = 4.5V
IOH = –2.5mA, VCC = 4.5V
IOH = –400µA, VCC = 4.5V
A9 = VID
A9 = VID
Doc. No. 1084, Rev. H
4
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DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and EEPROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation.

FEATURES
■ Fast Read Access Time: 90/120/150 ns
■ Low Power CMOS Dissipation:
   –Active: 30 mA max (CMOS/TTL levels)
   –Standby: 1 mA max (TTL levels)
   –Standby: 100 µA max (CMOS levels)
■ High Speed Programming:
   –10 µs per byte
   –1 Sec Typ Chip Program
■ 12.0V ± 5% Programming and Erase Voltage
■ Electronic Signature
■ Commercial, Industrial and Automotive Temperature Ranges
■ Stop Timer for Program/Erase
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
   –32-pin DIP
   –32-pin PLCC
   –32-pin TSOP ( 8 x 20)
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ "Green" Package Options Available

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