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CAT28F512G-12T View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part NameCAT28F512G-12T Catalyst
Catalyst Semiconductor => Onsemi Catalyst
Description512K-Bit CMOS Flash Memory
CAT28F512G-12T Datasheet PDF : 15 Pages
First Prev 11 12 13 14 15
CAT28F512
Figure 7. Programming Algorithm(1)
START
PROGRAMMING
APPLY VPPH
INITIALIZE
ADDRESS
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
WRITE PROG. CMD
ADDR AND DATA
BUS
OPERATION COMMAND
COMMENTS
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
1ST WRITE
CYCLE
WRITE
SETUP
DATA = 40H
2ND WRITE PROGRAM VALID ADDRESS AND DATA
CYCLE
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE PROGRAM
CYCLE
VERIFY
DATA = C0H
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
VERIFY
NO
DATA ?
YES
INCREMENT
ADDRESS
NO
LAST
ADDRESS?
YES
WRITE READ
COMMAND
NO
INC
PLSCNT
= 25 ?
YES
READ
STANDBY
READ BYTE TO VERIFY
PROGRAMMING
COMPARE DATA OUTPUT
TO DATA EXPECTED
1ST WRITE
CYCLE
READ
DATA = 00H
SETS THE REGISTER FOR
READ OPERATION
APPLY VPPL
APPLY VPPL
STANDBY
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1084, Rev. H
12
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DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and EEPROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation.

FEATURES
■ Fast Read Access Time: 90/120/150 ns
■ Low Power CMOS Dissipation:
   –Active: 30 mA max (CMOS/TTL levels)
   –Standby: 1 mA max (TTL levels)
   –Standby: 100 µA max (CMOS levels)
■ High Speed Programming:
   –10 µs per byte
   –1 Sec Typ Chip Program
■ 12.0V ± 5% Programming and Erase Voltage
■ Electronic Signature
■ Commercial, Industrial and Automotive Temperature Ranges
■ Stop Timer for Program/Erase
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
   –32-pin DIP
   –32-pin PLCC
   –32-pin TSOP ( 8 x 20)
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ "Green" Package Options Available

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