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CAT28F512G-12T View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part NameCAT28F512G-12T Catalyst
Catalyst Semiconductor => Onsemi Catalyst
Description512K-Bit CMOS Flash Memory
CAT28F512G-12T Datasheet PDF : 15 Pages
First Prev 11 12 13 14 15
CAT28F512
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
VCC POWER-UP
& STANDBY
SETUP PROGRAM
COMMAND
LATCH ADDRESS
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS
tAH
CE (E)
tCS
tCH
tCH
tCH
tCS
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
WE (W)
DATA (I/O)
tWP
tWP
tDH
tDH
tDS
tDS
HIGH-Z
DATA IN
= 40H
DATA IN
VCC 5.0V
0V
VPP VPPH
VPPL
tVPEL
tWP
tDS
tDH
DATA IN
= C0H
tOE
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
11
Doc. No. 1084, Rev. H
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DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and EEPROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation.

FEATURES
■ Fast Read Access Time: 90/120/150 ns
■ Low Power CMOS Dissipation:
   –Active: 30 mA max (CMOS/TTL levels)
   –Standby: 1 mA max (TTL levels)
   –Standby: 100 µA max (CMOS levels)
■ High Speed Programming:
   –10 µs per byte
   –1 Sec Typ Chip Program
■ 12.0V ± 5% Programming and Erase Voltage
■ Electronic Signature
■ Commercial, Industrial and Automotive Temperature Ranges
■ Stop Timer for Program/Erase
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
   –32-pin DIP
   –32-pin PLCC
   –32-pin TSOP ( 8 x 20)
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ "Green" Package Options Available

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