|CAT24C323J-30TE13||Supervisory circuits with I2C serial CMOS E2EPROM, precision reset controller and watchdog timer|
Catalyst Semiconductor => Onsemi
|CAT24C323J-30TE13 Datasheet PDF : 12 Pages |
The CAT24CXXX supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24CXXX
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
(1) Data transfer may be initiated only when the bus is
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24CXXX monitors the
SDA and SCL lines and will not respond until this
condition is met.
Figure 5. Acknowledge Timing
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
The Master begins a transmission by sending a START
condition. The Master sends the address of the particu-
lar slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
The next three bits are don’t care. The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera-
tion is selected.
After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the state of the R/W bit.
Figure 6. Slave Address Bits
1 0 1 0 X X X RW
Doc. No. 25084-00 12/98
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