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CAT24C323J-25TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

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CAT24C323J-25TE13 Datasheet PDF : 12 Pages
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Advanced
CAT24C323/643
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
VCC=2.7V - 6V
Min. Max.
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
VCC=4.5V - 5.5V
Min.
Max.
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
tPUR
Power-up to Read Operation
1
tPUW
Power-up to Write Operation
1
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
tWR
Write Cycle Time
10
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
Doc. No. 25084-00 12/98
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