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AT25128-10CC-1.8 View Datasheet(PDF) - Atmel Corporation

Part NameAT25128-10CC-1.8 Atmel
Atmel Corporation Atmel
DescriptionSPI Serial EEPROMs
AT25128-10CC-1.8 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Writes are only allowed to sections of the memory which
are not block-protected.
Note:
When the WPEN bit is hardware write protected, it can-
not be changed back to “0”, as long as the WP pin is held
low.
Table 5. WPEN Operation
Protected
WPEN WP WEN Blocks
0
X
0
Protected
0
X
1
Protected
1
Low
0
Protected
1
Low
1
Protected
X
High
0
Protected
X
High
1
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
READ SEQUENCE (READ): Reading the AT25128/256
via the SO (Serial Output) pin requires the following
sequence. After the CS line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by
the byte address to be read (Refer to Table 6). Upon com-
pletion, any data on the SI line will be ignored. The data
(D7-D0) at the specified address is then shifted out onto
the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The READ
sequence can be continued since the byte address is auto-
matically incremented and data will continue to be shifted
out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the
entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the
AT25128/256, two separate instructions must be executed.
First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruc-
tion may be executed. Also, the address of the memory
location(s) to be programmed must be outside the pro-
tected address field location selected by the Block Write
Protection Level. During an internal write cycle, all com-
mands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After
the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte
address and the data (D7-D0) to be programmed (Refer to
Table 6). Programming will start after the CS pin is brought
high. (The LOW to High transition of the CS pin must occur
during the SCK low time immediately after clocking in the
D0 (LSB) data bit.
The READY/BUSY status of the device can be determined
by initiating a READ STATUS REGISTER (RDSR) Instruc-
tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro-
gramming cycle.
The AT25128/256 is capable of a 64-byte PAGE WRITE
operation. After each byte of data is received, the five low
order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more
than 64-bytes of data are transmitted, the address counter
will roll over and the previously written data will be overwrit-
ten. The AT25128/256 is automatically returned to the write
disable state at the completion of a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the
device will ignore the Write instruction and will return to the
standby state, when CS is brought high. A new CS falling
edge is required to re-initiate the serial communication.
Table 6. Address Key
Address
AT25128
AT25256
AN
Don’t Care Bits
A13 - A0
A15 - A14
A14 - A0
A15
8
AT25128/256
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Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256), and 8-pin Leadless Array (AT25128/256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low Voltage and Standard Voltage Operation
   – 5.0 (VCC = 4.5V to 5.5V)
   – 2.7 (VCC = 2.7V to 5.5V)
   – 1.8 (VCC = 1.8V to 3.6V)
• 3 MHz Clock Rate
• 64-Byte Page Mode and Byte Write Operation
• Block Write Protection
   – Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
• Self-Timed Write Cycle (5 ms Typical)
• High Reliability
   – Endurance: 100,000 Write Cycles
   – Data Retention: >200 Years
   – ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP, and 8-Pin Leadless Array Packages

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