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AT25128-10CC-1.8 View Datasheet(PDF) - Atmel Corporation

Part NameAT25128-10CC-1.8 Atmel
Atmel Corporation Atmel
DescriptionSPI Serial EEPROMs


AT25128-10CC-1.8 Datasheet PDF : 17 Pages
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AT25128/256
Functional Description
The AT25128/256 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25128/256 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low CS
transition..
Table 1. Instruction Set for the AT25128/256
Instruction Instruction
Name
Format
Operation
WREN
0000 X110 Set Write Enable Latch
WRDI
0000 X100 Reset Write Enable Latch
RDSR
0000 X101 Read Status Register
WRSR
0000 X001 Write Status Register
READ
0000 X011 Read Data from Memory Array
WRITE
0000 X010 Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X
X
X
BP1 BP0 WEN RDY
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 2 (BP0) See Table 4.
Bit 3 (BP1) See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7
(WPEN)
See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25128/256 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any
selected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits
Array Addresses
Protected
Level
BP1
BP0
AT25128
AT25256
0
0
0
None
None
1(1/4)
0
1
3000 - 3FFF 6000 - 7FFF
2(1/2)
1
0
2000 - 3FFF 4000 - 7FFF
3(All)
1
1
0000 - 3FFF 0000 - 7FFF
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
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Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256), and 8-pin Leadless Array (AT25128/256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low Voltage and Standard Voltage Operation
   – 5.0 (VCC = 4.5V to 5.5V)
   – 2.7 (VCC = 2.7V to 5.5V)
   – 1.8 (VCC = 1.8V to 3.6V)
• 3 MHz Clock Rate
• 64-Byte Page Mode and Byte Write Operation
• Block Write Protection
   – Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
• Self-Timed Write Cycle (5 ms Typical)
• High Reliability
   – Endurance: 100,000 Write Cycles
   – Data Retention: >200 Years
   – ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP, and 8-Pin Leadless Array Packages

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