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ADS7870 View Datasheet(PDF) - Burr-Brown -> Texas Instruments

Part NameDescriptionManufacturer
Burr-Brown -> Texas Instruments BURR-BROWN
ADS7870 Datasheet PDF : 27 Pages
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The ADS7870 has eight analog-signal input pins, LN0
through LN7. These pins are connected to a network of
analog switches (the “MUX” block in Figure 1). The switches
are controlled by four bits in the Gain/Mux register.
LN0 through LN7 can be configured as 8 single ended inputs
or 4 differential inputs. Some mux combination examples
are shown in Figure 7. The differential polarity of the input
pins can be changed with the M2 bit in the MUX address.
This feature allows reversing the polarity of the conversion
result without having to physically reverse the input connec-
tions to the ADS7870.
For linear operation, the input signal at any of the LN0
through LN7 pins can range between GND – 0.2V and VDD
+ 0.2V. The polarity of the differential signal can be changed
through commands written to Gain/Mux register, but each
line must remain within the linear input common mode
voltage range as described below.
Inputs LN0 through LN7 have ESD protection circuitry as
the first active elements on the chip. These contain protec-
tion diodes connected to VDD and GND that remain reverse
biased under normal operation. If input voltages are ex-
pected beyond the absolute maximum voltage range it is
necessary to add resistance in series with the input to limit
the current to 10mA or less.
The conversion clock (CCLK) and signals derived from it
are used by the voltage reference, the PGA, and the A/D
converter. The PGA and the A/D use the same clock signal.
These clocks are associated with the OSC ENABLE and
CCLK pins as well as the OSCE and OSCR bits in the
Ref/Oscillator Configuration Register (register 7). CCLK
can be either an input pin or an output pin. When the OSC
ENABLE pin is low (OSC ENABLE = “0”), the CCLK pin
is an input and the ADS7870 uses an applied external clock
for the conversion process. When OSC ENABLE = “1”, the
ADS7870 uses an internal 2.5MHz oscillator as the conver-
sion clock. This clock signal appears as an output on the
CCLK pin.
The ADS7870 can be programmed to divide the CCLK
before it is applied to the A/D converter and PGA. This
allows a higher frequency system clock, such as the SCLK,
to be used synchronously to control the A/D converter
operation. The frequency division constant is controlled by
2 bits (CDF1 and CDF0) in the ADC Control Register.
Division factors (DF) of 1, 2, 4, and 8 are available. The
signal that is actually applied to the PGA and A/D is DCLK,
where DCLK = CCLK/DF.
The CCLK pin can be made either an input or an output and
is convenient in situations where several ADS7870s are used
in the same application. One ADS7870 can be made the
conversion clock master (CCLK made an output) and all the
other ADS7870s can be slaved to it (their pins made inputs).
This can potentially reduce A/D conversion errors caused by
clock and other systems noise.
The ADS7870 has both maximum and minimum DCLK
frequency constraints (DCLK = CCLK/DF). The maximum
DCLK is 2.5MHz. The minimum DCLK frequency applied
to the PGA, reference and A/D is 100kHz.
The internally generated VREF of the ADS7870 is based on
a band-gap voltage reference. The ADS7870 uses a unique
(patent pending) switched capacitor implementation of the
band-gap reference. The circuit has curvature correction for
VREF drift. The reference may be software configured for
output voltages of 1.15V, 2.048V or 2.5V.
The amplifier inside the reference circuit has very limited
output current capability. A separate buffer amplifier must
be used to supply any load current. The internal buffer
amplifier can supply typically up to 20mA and sink up to
20µA. The temperature compensation of the onboard refer-
ence is adjusted with the reference buffer in the circuit.
Performance is specified in this configuration.
The programmable gain amplifier (PGA) provides gains of
1, 2, 4, 5, 8, 10, 16, and 20V/V. The PGA is a single supply,
rail-to-rail input, auto-zeroed, capacitor based instrumenta-
tion amplifier. PGA gain is set by bits G2 through G0 of
Register 4.
Register 2 is a read only register that is used to report any out
of range conditions at the PGA input or output during the
convert cycle. The logical “OR” of these signals is available
as the least significant bit of the A/D output register 0.
Testing bit D0 of the A/D output register will indicate out of
range conditions as described in the section which details the
register contents.
The 12-bit A/D converter in the ADS7870 is a successive
approximation type. The output of the converter is 2’s
complement format and can be read through the serial
interface MSB first or LSB first. A plot of Output Codes vs
Input Voltage is shown in Figure 2. With the input multi-
plexer configured for differential input the A/D output codes
range from –2048 for VIN = –VREF/G to 2047 for VIN =
(+VREF –1VLSB)/G. With the input multiplexer configured
for single-ended inputs the A/D output codes range from
0 to 2047 for VIN = 0 to (+VREF – 1VLSB)/G.
A conversion cycle requires 48 DCLK cycles (DCLK =
CCLK/DF). These signals are described in the Conversion
Clock section that follows.
Operation of the PGA requires 36 DCLK cycles. During the
PGA portion, the common mode voltage of the input source
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