|ADC0808S250||Single 8-bit ADC, up to 125 MHz or 250 MHz|
|ADC0808S250 Datasheet PDF : 23 Pages |
Single 8-bit ADC, up to 125 MHz or 250 MHz
D0 to D7
CCS (fclk / 2)
Fig 6. Complete conversion signal timing diagram using CCS
7.5 Full-scale input selection
The ADC0808S has an internal reference circuit which can be overruled by an external
reference voltage. This can be done with the full-scale reference voltage (Vref(fs))
according to Table 9.
The ADC provides the required common-mode voltage on pin CMADC. In case of internal
regulation, the regulator output voltage on pin CMADC is 0.95 V.
Table 9. Full-scale input selection
Full-scale reference voltage
Maximum peak-to-peak input
The internal reference circuit is enabled by connecting pin FSIN to ground. The
common-mode output voltage VO(cm) on pin CMADC will then be 0.95 V, and the
maximum peak-to-peak input voltage Vi(p-p)(max) will be 2.0 V; see Figure 7 and Figure 8.
The ADC full-scale input selection principle is shown in Figure 9.
Product data sheet
Rev. 03 — 24 February 2009
© NXP B.V. 2009. All rights reserved.
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