Single 8-bit ADC, up to 125 MHz or 250 MHz
7.3 Timing output
D0 to D7
Fig 5. Output timing diagram (CCS not selected)
7.4 Timing complete conversion signal
The ADC0808S generates an adjustable clock output signal on pin CCS called Complete
Conversion Signal, which can be used to control the acquisition of converted output data
to the digital circuit connected to the ADC0808S output data bus.
Two logic input pins DEL0 and DEL1 control the delay of the edge of the CCS signal to
achieve an optimal position in the stable, usable zone of the data as shown in Figure 6.
Table 7. Complete conversion signal selection
active; see Table 13
Pin CCSSEL selects the CCS frequency; see Table 8.
Table 8. Complete conversion signal frequency selection
HIGH or not connected
CCS frequency (fCCS)
fclk / 2
Product data sheet
Rev. 03 — 24 February 2009
© NXP B.V. 2009. All rights reserved.
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