datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ACE1202BV View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
ACE1202BV Datasheet PDF : 39 Pages
First Prev 31 32 33 34 35 36 37 38 39
Figure 34: Crystal (a) and RC (b) Oscillator Diagrams
a)
CKI
(G1)
CKO
(G0)
b)
CKI
(G1)
CKO
(G0)
1M
R
VCC
33pF
C
33pF
15.0 HALT Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the LD M, #
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 9) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes. Immedi-
ately after exiting HALT, software must clear the Power Mode
Clear (PMC) register by only using the LD M, #instruction. (See
Figure 36)
Figure 35: HALT Register Definition
Bit 7
undefined
Bit 6
undefined
Bit 5
undefined
Bit 4
undefined
17.0 IDLE Mode
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the LD M, #instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device automatically wakes from IDLE mode by the Timer 0
overflow every 8192 cycles (see Section 6). Before entering IDLE
mode, software must clear the WKEN register to disable the MIW
block. Once a wake from IDLE mode is triggered, the core will begin
normal operation by the next clock cycle. Immediately after exiting
IDLE mode, software must clear the Power Mode Clear (PMC)
register by using only the "LD M, #" instruction. (See Figure 37)
Bit 3
undefined
Bit 2
undefined
Bit 1
EIDLE
Bit 0
EHALT
Figure 36: Recommended HALT Flow
Figure 37: Recommended IDLE Flow
Normal Mode
Normal Mode
LD HALT, #01h
Multi-Input
Wakeup
Halt
LD PMC, #00h
Resume
Normal Mode
CLR WKEN
LD HALT, #02h
Timer 0
Overflow
IDLE
LD PMC, #00h
Resume
Normal Mode
34
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]