datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ACE1202M View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
ACE1202M Datasheet PDF : 39 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
10.0 I/O Port
The eight I/O pins (six on 8-pin package option) are bi-directional
(see Figure 28) with the exception of G3 which is always an input
with weak pull-up. The bi-directional I/O pins can be individually
configured by software to operate as high-impedance inputs, as
inputs with weak pull-up, or as push-pull outputs. The operating
state is determined by the contents of the corresponding bits in the
data and configuration registers. Each bi-directional I/O pin can be
used for general purpose I/O, or in some cases, for a specific
alternate function determined by the on-chip hardware.
10.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
Figure 28: PORTG Logic Diagram
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pull-
up or a high-impedence input. Table 14 provides details of the port
configuration options. The port configuration and data registers
can both be read from or written to. Reading PORTGP returns the
value of the port pins regardless of how the pins are configured.
Since this device supports MIW, PORTG inputs have Schmitt
triggers.
GXPULLEN
GXBUFEN
GXOUT
PADGX
GXIN
Figure 29: I/O Register bit assignments (PORTGC,PORTGD, PORTGD)
Bit 7
Bit 6
13G7
13G6
13 Available only on the 14-pin package option
14 G3 is always an input with weak pull-up
Bit 5
G5
Bit 4
G4
Bit 3
14G3
Bit 2
G2
Bit 1
G1
Table 14: I/O configuration options
Configuration Bit
0
0
1
1
Data Bit
0
1
0
1
Port Pin Configuration
High-impedence input (TRI-STATE input)
Input with pull-up (weak one input)
Push-pull zero output
Push-pull one output
Bit 0
G0
29
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]