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ACE1202E View Datasheet(PDF) - Fairchild Semiconductor

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ACE1202E Datasheet PDF : 39 Pages
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Figure 24: HBC signals for one byte message in PWM format
Condition:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
TXBUSY
START/STOP
ShiftCLK
OCFLAG
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
SYNC
Period
"0"
"0"
"1"
"0"
"1"
"0"
"0"
"1"
"0"
¡
Figure 25: Sending series of encoded messages
Conditions:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52 , 0x92
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
TXBUSY
START/STOP
ShiftCLK
Software must set the START bit while OCFLAG is set in
order to send another message without introducing a delay.
STOP bit clear,
transmission ends.
OCFLAG
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
SYNC
Period
"0" "0" "1" "0" "1" "0" "0" "1" "0" "1" "0" "0" "1" "0" "0" "1" "0"
27
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
 

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