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ACE12022BMX View Datasheet(PDF) - Fairchild Semiconductor

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ACE12022BMX Datasheet PDF : 39 Pages
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8.0 Hardware Bit-Coder (ACE1202-2 only)
The ACE1202-2 contains a dedicated hardware bit-encoding
peripheral block, Hardware Bit-Coder (HBC), for IR/RF data
transmission (see Figure 21.) The HBC is completely software
programmable and can be configured to emulate various bit-
encoding formats. The software developer has the freedom to
encode each bit of data into a desired pattern and output the
encoded data at the desired frequency through either the G2 or G5
output (TX) ports.
The HBC contains six 8-bit memory-mapped configuration regis-
ters PSCALE, HPATTERN, LPATTERN, BPSEL, HBCNTRL, and
DAT0. The registers are used to select the transmission fre-
quency, store the data bit-encoding patterns, configure the data
bit-pattern/frame lengths, and control the data transmission flow.
To select the IR/RF transmission frequency, an 8-bit divide
constant must be written into the IR/RF Pre-scalar (PSCALE)
register. The IR/RF transmission frequency generator divides the
1MHz instruction clock down by 4 and the PSCALE register is
used to select the desired IR/RF frequency shift. Together, the
transmission frequency range can be configured between 976Hz
(PSCALE = 0xFF) and 125kHz (PSCALE = 0x01). Upon a reset,
the PSCALE register is initialized to zero disabling the IR/RF
transmission frequency generator. However, once the PSCALE
register is programmed, the desired IR/RF frequency is main-
tained as long as the device is powered.
Once the transmission frequency is selected, the data bit-encod-
ing patterns must be stored in the appropriate registers. The HBC
contains two 8-bit bit-encoding pattern registers, High-pattern
(HPATTERN) and Low-pattern (LPATTERN). The encoding pat-
tern stored in the HPATTERN register is transmitted when the
data bit value to be encoded is a 1. Similarly, the pattern stored in
the LPATTERN register is transmitted when the data bit value to
be encoded is a 0. The HBC transmits each encoded pattern MSB
first.
The number of bits transmitted from the HPATTERN and
LPATTERN registers is software programmable through the Bit
Period Configuration (BPSEL) register (see Figure 22). During the
transmission of HPATTERN, the number of bits transmitted is
configured by BPH[2:0] (BPSEL[2:0]) while BPL[2:0] (BPSEL[5:3])
configures the number of transmitted bits for the LPATTERN. The
HBC allows from 2 (0x1) to 8 (0x7) encoding pattern bits to be
transmitted from each register. Upon a reset, BPSEL is initially 0
disabling the HBC from transmitting pattern bits from either
register.
The Data (DAT0) register is used to store up to 8 bits of data to be
encoded and transmitted by the HBC. This data is shifted, bit by
bit, MSB to LSB into a 1-bit decision register. If the active bit shifted
into the decision register is 1, the pattern in the HPATTERN
register is shifted out of the output port. Similarly, if the active bit
is 0 the pattern in the LPATTERN register is shifted out.
The HBC control (HBCNTRL) register is used to configure and
control the data transmission. HBCNTRL is divided in 5 different
controlling signal FRAME[2:0], IOSEL, TXBUSY, START/STOP,
and OCFLAG (see Figure 23.)
FRAME[2:0] selects the number of bits of DAT0 to encode and
transmit. The HBC allows from 2 (0x1) to 8 (0x7) DAT0 bits to be
encoded and transmitted. Upon a reset, FRAME is initialized to
zero disabling the DAT0s decision register transmitting no data.
The IOSEL signal selects the transmission to output (TX) through
either port G2 or G5. If IOSEL is 1, G5 is selected as the output port
otherwise G2 is selected.
The TXBUSY signal is read only and is used to inform software
that a transmission is in progress. TXBUSY goes high when the
encoded data begins to shift out of the output port and will remains
high during each consecutive DAT0 frame bit transmission (see
Figure 25). The HBC will clear the TXBUSY signal when the last
DAT0 encoded bit of the frame is transmitted and the STOP signal
is 0.
The START / STOP signal controls the encoding and transmission
process for each data frame. When software sets the START /
STOP bit the DAT0 frame transmission process begins. The
START signal will remain high until the beginning of the last
encoded DAT0 frame bit transmission. The HBC then clears the
START / STOP bit allowing software to either continue with a new
DAT0 frame transmission or stop the transmission all together
(see Figure 25). If TXBUSY is 0 when the START signal is
enabled, a synchronization period occurs before any data is
transmitted lasting the amount of time to transmit a 0 encoded bit
(see Figure 24).
The OCFLAG signal is read only and goes high when the last
encoded bit of the DAT0 frame is transmitting. The OCFLAG
signal is used to inform software that the DAT0 frame transmission
operation is completing (see Figure 25). If multiple DAT0 frames
are to be transmitted consecutively, software should poll the
OCFLAG signal for a 1. Once OCFLAG is 1, DAT0 must be reload
and the START / STOP bit must be restored to 1 in order to begin
the new frame transmission without interruptions (the synchroni-
zation period). Since OCFLAG remains high during the entire last
encoded DAT0 frame bit transmission, software should wait for
the HBC to clear the OCFLAG signal before polling for the new
OCFLAG high pulse. If new data is not reloaded into DAT0 and the
START signal (STOP is active) is not set before the OCFLAG is
0, the transmission process will end (TXBUSY is cleared) and a
new process will begin starting with the synchronization period.
Figure 24 and 25 shows how the HBC performs its data encoding.
In the example, two frames are encoded and transmitted consecu-
tively with the following bit encoding format specification:
1. Transmission frequency = 62.5KHz
2. Data to be encoded = 0x52, 0x92 (all 8-bits)
3. Each bit should be encoded as a 3-bit binary value, 1=
110b and 0= 100b
4. Transmission output port : G2
To perform the data transmission, software must first initialize the
PSCALE, BPSEL, HPATTERN, LPATTERN, and DAT0 registers
with the appropriate values.
LD PSCALE, #03H
; (1MHz ÷ 4) ÷ 4 = 62.5KHz
LD BPSEL, #012H
; BPH = 2, BPL = 2 (3 bits each)
LD HPATTERN, #0C0H
; HPATTERN = 0xC0
LD LPATTERN, #090H
; LPATTERN = 0x90
LD DAT0, #052H
; DAT0 = 0x52
Once the basic registers are initialized, the HBC can be started.
(At the same time, software must set the number of data bits per
data frame and select the desired output port.)
LD HBCNTRL, #27H
; START / STOP = 1,
FRAME = 7, IOSEL = 0
25
ACE1202 Product Family Rev. B.1
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