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ACE1202BVMX View Datasheet(PDF) - Fairchild Semiconductor

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ACE1202BVMX Datasheet PDF : 39 Pages
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5.0 Timer 1
Timer 1 is a versatile 16-bit timer that can operate in one of four
modes:
Pulse Width Modulation (PWM) mode, which generates
pulses of a specified width and duty cycle
External Event Counter mode, which counts occurrences
of an external event
Standard Input Capture mode, which measures the
elapsed time between occurrences of external events
Difference Input Capture mode, which automatically
measures the difference between edges
Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit
auto-reload/capture register (T1RA), and an 8-bit control register
(T1CNTRL). All register are memory-mapped for simple access
through the core with both the 16-bit registers organized as a pair
of 8-bit register bytes {TMR1HI, TMR1LO} and {T1RAHI, T1RALO}.
Depending on the operating mode, the timer contains an external
input or output (T1) that is multiplexed with the I/O pin G2. By
12 and 13.
Table 12: TIMER1 Control Register (T1CNTRL)
T1CNTRL Register
Bit 7
Bit 6
Bit 5
Bit 4
Name
T1C3
T1C2
T1C1
T1C0
Bit 3
Bit 2
Bit 1
Bit 0
T1PND
T1EN
M4S1
-----------
default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,
and T1CNTRL is reset to 0x00.
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decre-
ments) every clock cycle. Depending on the operating mode, the
timers clock is either the instruction clock or a transition on the T1
input. In addition, occurrences of timer underflow (transitions from
0x0000 to 0xFFFF/T1RA value) can either generate an interrupt
and/or toggle the T1 output pin.
Timer 1s interrupt (TMRI1) can be enabled by interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, depending on the operating mode, the source of the
interrupt is a timer underflow and/or a timer capture.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timers
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, and start or
stop the timer. The T1CNTRL register bits are described in Tables
Function
Timer TIMER1 control bit 3 (see Table 13)
Timer TIMER1 control bit 2 (see Table 13)
Timer TIMER1 control bit 1 (see Table 13)
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 13)
Reserved
Table 13: TIMER1 Operating Modes
T1 T1 T1 M4
C3 C2 C1 S1
Timer Mode
Source
0
0
0
x MODE 2
0
0
1
x MODE 2
1
0
1
x MODE 1 T1 Toggle
1
0
0
x MODE 1 No T1 Toggle
0
1
0
x MODE 3 Captures: T1 Pos. edge
0
1
1
x MODE 3 Captures: T1 Neg. Edge
1
1
0
0 MODE 4 Difference Capture
1
1
0
1 MODE 4 Difference Capture
1
1
1
0 MODE 4 Difference Capture
1
1
1
1 MODE 4 Difference Capture
Interrupt A
TIMER1 Underflow
TIMER1 Underflow
Autoreload T1RA
Autoreload T1RA
Pos. T1 Edge
Neg. T1 Edge
Pos. to Neg.
Pos. to Pos.
Neg. to Pos.
Neg. to Neg.
Timer Counts On
T1 Pos. Edge
T1 Neg. Edge
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
19
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
 

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