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ACE1101MT8 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
MFG CO.
ACE1101MT8 Datasheet PDF : 33 Pages
Figure 26: Crystal (a) and RC (b) Oscillator Diagrams
a)
CKI
(G1)
CKO
(G0)
b)
CKI
(G1)
CKO
(G0)
1M
R
VCC
33pF
C
33pF
16.0 HALT Mode
The ACE1101 is placed into HALT by setting bit 0 of the HALT
mode register using the LD M, # instruction. The HALT enable bit
(Bit 0) is a write only bit and is automatically cleared on exiting halt.
Upon entering HALT, the internal oscillator, as well as all on-chip
systems, including Low battery detect and Brown out circuits, are
shut down. Prior to entering HALT, software should set the
appropriate wake-up I/O configuration. The device can only be
brought out of HALT by multi-input wake up. After wake up from
HALT, a 1ms startup delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes.
Immediately after exiting HALT, software must clear the Power
mode clear register also using a LD M, # instruction. See Figure
27 below.
Figure 27: Recommended HALT Flow
Normal Mode
LD HALT, #01h
17.0 IDLE Mode
In addition to HALT, the ACE1101 supports IDLE mode operation.
The IDLE mode is similar to HALT, except the internal oscillator,
Watchdog, and Timer0 remain active. Figure 28 shows the proper
sequence for software to initiate and recover from IDLE.
The ACE1101 is forced into IDLE by writing to bit 1 of the HALT
mode register using the LD M, # instruction. The idle enable bit (bit
1) is a write only bit and is automatically cleared on exiting IDLE.
The microcontroller resumes normal operation from the IDLE
mode when the T0PND bit (representing 8.192ms at an internal
clock frequency of 1MHz, tc = 1µs) of the IDLE timer is set.
The user has the option to interrupt after IDLE. In order to interrupt
after idle, software will need to make sure the interrupt enable
(T0INTEN) bit is set in the T0CNTRL register and also make sure
the global interrupt bit (G) is set in the status register. Once the
interrupt is serviced, software should reset the T0PND bit before
exiting the routine.
Immediately after coming out of IDLE, software must clear the
Power mode clear register by also using a LD M, # instruction.
Figure 28: Recommended IDLE Flow
Normal Mode
Halt
LD HALT, #02h
Multi-Input Wakeup
LD PMC, #00h
Resume
Normal Mode
IDLE
LD PMC, #00h
Resume
Normal Mode
ACE1101 Rev. C.8
31
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