datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ACE1101LVMT8X View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
ACE1101LVMT8X Datasheet PDF : 33 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
11.0 Low battery detect circuit
The Low Battery Detect (LBD) circuit sets the LBD bit in the LBD
register (see Figure 24) when VCC drops below the selected
threshold voltage. The threshold voltage can be adjusted from
2.4V to 3.0V ±10% using the three most significant bits of the LBD
register. The LBDEN (Low Battery Detect enable) bit in the
initialization register is used to enable or disable the low battery
detection.
The LBD bit is read only. If 0, it indicates that the VCC level is higher
than the desired threshold. If set to 1, it indicates that the VCC level
is below the desired threshold.
The LBD circuit is disabled during HALT mode. On exiting HALT
mode, the software must wait 10µs before reading the LBD bit to
ensure that the circuit has stabilized.
Voltage
Bat_trim2 Bat_trim1 Bat_trim0 Range
0
0
0
2.9 - 3.0
0
0
1
2.8 - 2.9
0
1
0
2.7 - 2.8
0
1
1
2.6 - 2.7
1
0
0
2.5 - 2.6
1
0
1
2.4 - 2.5
12.0 Brown-out detection circuit
The Brown-out detect circuit is used to reset the device when Vcc
falls below a 2.0V threshold. Once VCC rises above the 2.0V
threshold, a reset sequence will be generated. The Brown-out
Reset enable (BOREN) bit in the initialization register is used to
Table 14: CMODEx Bit Definition
CMODE1
0
0
1
1
CMODE0
0
1
0
1
enable or disable the brown-out detection. This bit must be set
after the device has been programmed.
Brown-out is not supported on 2.2/2.7V devices.
13.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset,
setting all I/Os to high impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is gener-
ated by any one of the following three conditions:
I Power-on RESET (as described in Section 14)
I Brown-out RESET (as described in Section 12)
I Watchdog RESET (as described in Section 7)
14.0 Power-on Reset
The Power-on RESET circuit is guaranteed to work if the rate of
rise of VDD is no slower than 10ms/1 volt. It is also necessary that
VDD starts from 0V.
15.0 CLOCK
The ACE1101 has an on-board oscillator trimmed to a frequency
of 2MHz, yielding a 1MHz frequency and a tolerance over tem-
perature, voltage, and device of ±10%. Upon power-up, the on-
chip oscillator runs continuously unless entering HALT mode.
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits. (See Table 14.) When the device is
driven using an external clock, the clock input to the device (G1/
CKI) can range between DC to 4MHz. For crystal configuration,
the output clock (CKO) is on the G0 pin. If an external crystal or
external RC is used, it will be internally divided by four (input
frequency/4) to yield an instruction clock cycle time of the corre-
sponding input frequency. If the device is configured for an
external square clock, it will not be divided. See Figure 26.
Clock Type
Internal 1 MHz clock
External square clock
External crystal/resonator
External RC clock
Figure 24: LBD Register Definition
Bit 7
Bat_trim2
Bit 6
Bat_trim1
Bit 5
Bat_trim0
Bit 4
undefined
Bit 3
undefined
Bit 2
Undefined
Bit 1
undefined
Bit 0
LBD
Figure 25: HALT Register Definition
Bit 7
undefined
Bit 6
undefined
Bit 5
undefined
Bit 4
undefined
Bit 3
undefined
Bit 2
undefined
Bit 1
EIDLE
Bit 0
EHALT
ACE1101 Rev. C.8
30
www.fairchildsemi.com
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]