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ACE1101LM8X View Datasheet(PDF) - Fairchild Semiconductor

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ACE1101LM8X Datasheet PDF : 33 Pages
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9.0 I/O Port
The six I/O pins are bi-directional (see Figure 21) with the
exception of G3 which is always an input with weak pull-up. The
bi-directional I/O pins can be individually configured by software
to operate as high-impedance inputs, inputs with weak pull-up, or
as push-pull outputs. The operating state is determined by the
contents of the corresponding bits in the data and configuration
registers. Each bi-directional I/O pin can be used for general
purpose I/O, or in some cases, for a specific alternate function
determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G5) have three memory port registers associ-
ated with them: a port configuration register (PORTGC), a port
Table 12: I/O configuration options
Configuration Bit
0
0
1
1
Data Bit
0
1
0
1
data register (PORTGD), and a port input register (PORTGP).
PORTGC is used to configure the pins as inputs or outputs. A pin
may be configured as an input by writing a 0or as an output by
writing a 1to its corresponding PORTGC bit. If a pin is configured
as an output, its PORTGD bit represents the state of the pin (1 =
logic high, 0 = logic low). If the pin is configured as an input, its
PORTGD bit selects whether the pin is a weak pull-up or a high-
impedence input. Table 12 provides details of the port configura-
tion options. The port configuration and data registers are both
read/writeable. Reading PORTGP returns the value of the port
pins regardless of how the pins are configured. Since this device
supports multi-input wakeup/interrupt, PORTG inputs have Schmitt
triggers.
Port Pin Configuration
High-impedence input (TRI-STATE output)
Input with pull-up (weak one output)
Push-pull zero output
Push-pull one output
Figure 21: PORTG Logic Diagram
Weak Pull-up Control
PORTGC
PORTGD
PORTGP
PINGX
ACE1101 Rev. C.8
27
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