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ACE1101LM8 View Datasheet(PDF) - Fairchild Semiconductor

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ACE1101LM8 Datasheet PDF : 33 Pages
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6.0 Timer 0
Timer 0 is a 12-bit idle timer. Upon power up or any reset, the timer
is reset to 0 and then counts up continuously based on the
instruction clock of 1MHz (1µs). Software cannot read from or
write to this timer. However, software can monitor the timer's
pending (T0PND) bit which is set every 8.192ms. The T0PND is
set each time the timer overflows (counts up to FFFh). After an
overflow, the timer will reset and restart its count up sequence.
Software can either poll the T0PND bit or vector to interrupt
routine. In order to interrupt on a T0PND, software will need to
make sure the interrupt enable (T0INTEN) bit is set in the
T0CNTRL register and also make sure the global interrupt bit (G)
is set in the status register. Once the timer interrupt is serviced,
software should reset the T0PND bit before exiting the routine.
The Timer 0 supports the following functions:
1. Exit from IDLE mode. (See Section 17 for details.)
2. Start up delay from halt mode.
3. Watchdog prescaler. (See Section 7 for details.)
The Timer 0 interrupt enable (T0INTEN) bit is a read/write bit. If set
to 0, interrupt requests from the Timer 0 are ignored. If set to 1,
interrupt requests are accepted. The T0INTEN bit is set to zero at
reset.
The T0PND (Timer 0 pending) bit is a read/write bit. If set to "1,"
it indicates that a Timer 0 interrupt is pending. This bit is set by a
Timer 0 overflow and is reset by software or reset.
The WKINTEN bit is used in the Multi-input wakeup block. (See
Section 8 for details.)
7.0 Watchdog timer
The 12-bit Timer 0 is also used to clock the watchdog timer. If the
WDEN bit in the initialization register is asserted, the watchdog
timer must be updated at least every 65,536 cycles but no sooner
than 4096 cycles since the last watchdog update. The watchdog
is updated through software by writing the value 0x1bh to the
WDSVR register (see Figure 19). The part will be reset automati-
cally if the watchdog is updated too frequently, or not frequently
enough. The WDEN bit can only be set while the device is in
programming mode. Once set, the watchdog will always be
powered up enabled. Software cannot disable the watchdog. The
watchdog timer can be disabled in programming mode by reset-
ting the WDEN bit as long as the global write protect feature is not
enabled (WDIS).
WARNING
Ensure that the Watchdog timer has been updated before entering
IDLE mode.
Figure 18: Timer 0 Control Register (T0CNTRL)
Bit 7
WKINTEN
Bit 6
x
Bit 5
x
Bit 4
x
Bit 3
x
Bit 2
x
Bit 1
T0PND
Bit 0
T0INTEN
Figure 19: Watchdog Service Register (WDSVR)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
1
ACE1101 Rev. C.8
25
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