datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ACE1101LV View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
ACE1101LV Datasheet PDF : 33 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
5.2 Mode 1: Pulse Width Modulation Mode
In the Pulse Width Modulation (PWM) mode, the timer counts down
at the instruction clock rate. When an underflow occurs, the timer
register is reloaded from T1RA, and decrementing proceeds from
the loaded value. At every underflow interrupt, software should load
the T1RA register with the alternate PWM value.
The timer can be configured to toggle the T1 output bit upon
underflow. This results in the generation of a clock signal on T1 with
the width and duty cycle controlled by the values stored in the T1RA.
A block diagram of the timer operating in the PWM mode is shown
In Figure 15.
There is one interrupt associated with the timer, designated the
Timer1 interrupt. The interrupt is maskable by the enable bit T1EN.
T1 will generate an interrupt with every timer underflow if the timer
interrupt is enabled by T1EN. The interrupt will be simultaneous
with every rising and falling edge of the PWM output. Generating
interrupts only on rising-, or falling edges of T1 is achievable
through appropriate handling of T1EN by the user software.
When an underflow occurs that causes a timer reload from T1RA,
the interrupt pending flag bit T1PNDA is set. A CPU interrupt occurs
if T1EN bit and the G (Global Interrupt enable) bit of the Status
register is set. The interrupt service routine must reset the pending
bit and perform whatever processing is necessary at the interrupt
point.
Figure 15: Pulse Width Modulation Mode
Timer
Underflow
Interrupts
The following steps can be used to operate the timer in the PWM
mode. In this example, the T1 output pin is toggled with every
timer underflow, and the highand lowtimes for the T1 output
can be set to different values. The T1 output can start out either
high or low; the instructions below are for starting with the T1
output high. (Follow the instructions in parentheses to start the
T1 output low.)
1. Configure the T1 pin as an output by setting bit 2 of
PORTGC.
2. Initialize the T1 pin value to 1 (or 0) by setting (or clearing)
bit 2 of PORTGD.
3. Load the PWM highor lowtime into the timer register.
4. Load the PWM lowor hightime into the T1RA register.
5. Write the appropriate value to the timer control bits T1C3-
T1C2- T1C1 to select the PWM mode, and to toggle the T1
output with every timer underflow (see Table 11).
6. Set the T1C0 bit to start the timer.
7. Upon every underflow interrupt load T1RA with alternate
values, ON or OFF time.
If the user wishes to generate an interrupt on timer output
transitions, reset the pending flags and then enable the interrupt
using T1EN. The G bit must also be set. The interrupt service
routine must reset the pending flag and perform whatever
processing is desired.
16-bit Autoreload
Register T1RA
T1
Data
Latch
BUS
16-bit Timer
Instruction
Clock
ACE1101 Rev. C.8
22
www.fairchildsemi.com
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]