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ACE1101LM8 View Datasheet(PDF) - Fairchild Semiconductor

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ACE1101LM8 Datasheet PDF : 33 Pages
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4.5 Memory
The ACE1101 device has 64 bytes of SRAM and 64 bytes of
EEPROM available for data storage. The microcontroller also has
a 1K byte EEPROM block for program storage. The user can read/
write to RAM and data EEPROM but cannot perform writes to the
1K byte EEPROM array which is protected from writes during
normal mode operations. The instruction data in the program
EEPROM array can only be rewritten when the device is in
program mode and if the initialization register bit WDIS (write
disable) is not set.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the R bit of the status register, then 2) executing
the appropriate write instruction. A "1" on the R bit indicates the
data EEPROM block is ready to perform the next write. A "0"
indicates the data EEPROM is busy. The data EEPROM array will
reset the R bit on the completion of a write cycle. Attempts to read,
write, or enter HALT while the data EEPROM is busy (R bit = "0")
could affect the current data being written.
4.6 Initialization Registers
The ACE1101 has two 8-bit wide initialization registers. These
registers are read from memory space on power-up and initializes
certain on-chip peripherals. Figure 14 provides a detailed descrip-
tion of Initialization Register 1. The Initialization Register 2 is used
to trim the internal oscillator. This register is pre-programmed in
the factory to yield a 1MHz internal clock.
Both Initialization Registers 1 and 2 are read/writable in program-
ming mode. However, retrimming the internal oscillator (writing to
the Initialization Register 2) is discouraged.
Figure 14: Initialization Register 1
Bit 7
CMODE0
Bit 6
CMODE1
Bit 5
WDEN
Bit 4
BOREN
Bit 3
LBDEN
Bit 2
UBD
Bit 1
WDIS
(0) RDIS
(1) WDIS
(2) UBD
(3) LBDEN
(4) BOREN
(5) WDEN
(6) CMODE1
(7) CMODE0
If set, disables attempts to read any EEPROM contents in programming mode
If set, disables attempts to write any EEPROM contents in programming mode
If set, the device will not allow writes to occur in the upper block of data EEPROM
1 enables LBD, 0 disables LBD
If set, allows a brown-out reset to occur if Vcc is so low that a reliable
EEPROM write cannot take place
If set, enables the on-chip processor watchdog circuit
Clock mode select bit one
Clock mode select bit zero
Note 1: If WDIS and RDIS bits are both set, the device will no longer be able to be placed into program mode.
Note 2: If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits could be reset.
Bit 0
RDIS
ACE1101 Rev. C.8
20
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