datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

MC33661PEF View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
View to exact match
MC33661PEF Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN OUTPUT TIMING CHARACTERISTICS FOR NORMAL MODE
Dominant Propagation Delay Time TXD to LIN (6)
Measurement Threshold (50% TXD to 58.1% VSUP)
Measurement Threshold (50% TXD to 28.4% VSUP)
Recessive Propagation Delay Time TXD to LIN (6)
Measurement Threshold (50% TXD to 42.2% VSUP)
Measurement Threshold (50% TXD to 74.4% VSUP)
s
t DOM (MIN)
50
t DOM (MAX)
50
s
t REC (MIN)
50
t REC (MAX)
50
Propagation Delay Time Symmetry
t DOM (MIN) to t REC (MAX)
t DOM (MAX) to t REC (MIN)
s
dt1
- 10.44
dt2
- 10.44
8.12
8.12
LIN OUTPUT TIMING CHARACTERISTICS FOR SLOW MODE
Dominant Propagation Delay Time TXD to LIN (6)
Measurement Threshold (50% TXD to 61.6% VSUP)
Measurement Threshold (50% TXD to 25.1% VSUP)
Recessive Propagation Delay Time TXD to LIN (6)
Measurement Threshold (50% TXD to 38.9% VSUP)
Measurement Threshold (50% TXD to 77.8% VSUP)
t DOM (MIN)
t DOM (MAX)
t REC (MIN)
t REC (MAX)
s
100
100
s
100
100
Propagation Delay Time Symmetry
t DOM (MIN) to t REC (MAX)
t DOM (MAX) to t REC (MIN)
s
dt1S
- 21.88
dt 2S
- 21.88
17.44
17.44
LIN OUTPUT DRIVER FAST MODE
LIN Fast Slew Rate (Programming Mode)
Fast Slew Rate
dv/dt fast
V/s
15
LIN PIN
Over-current Shutdown Delay Time (7)
LIN RECEIVER CHARACTERISTICS
Receiver Dominant Propagation Delay Time (8)
LIN LOW to RXD LOW
Receiver Recessive Propagation Delay Time (8)
LIN HIGH to RXD HIGH
t OV-DELAY
10
s
t RL
s
3.5
6.0
t RH
s
3.5
6.0
Receiver Propagation Delay Time Symmetry
t RL - t RH
t R-SYM
s
- 2.0
2.0
Notes
6. 7.0 V VSUP 18 V. Bus load R0 and C0: 1.0 nF/1.0 k, 6.8 nF/660 , 10 nF/500 .
7. This parameter is guaranteed by design; however, it is not production tested.
8. Measured between LIN signal threshold VLINL or VLINH and 50% of RXD signal.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33661
7
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]