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VV5300 View Datasheet(PDF) - Vision

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VV5300 Datasheet PDF : 43 Pages
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VV5300 Sensor
Qualifying the Output Data
Data is output from VV5300 in a continuous stream. By utilising signals, like FST, and key events, like the
start of a line or the end of line, the user can sample and display the image data. QCK is used to sample the
data, as described in the previous section. By default the falling edge of QCK will sample the data, however
it is possible to use both the rising and falling edges of a slow QCK QCKS to sample the data.
Different sections of the frame can be enabled by QCK. The options, which are selected via setup register4
in the serial interface, are as follows, firstly the QCK can be disabled, therefore no data will be qualified. This
is the default option.
The second option is to have the QCK free running where all the data is qualified.
The third option is to only qualify the image data, which also includes the 2 black calibration monitor lines,
lines 1 and 2 in the frame. This option is further complicated in that extra black lines and the extra border
pixels/lines can be enabled giving the following 4 options:
1. Black lines (1-2) plus image (160 pixels by 120 lines)
2. Black lines (1-8) plus image (160 pixels by 120 lines)
3. Black lines (1-2) plus image (164 pixels by 124 lines)
4. Black lines (1-8) plus image (164 pixels by 124 lines)
The final option is to qualify the embedded frame control sequences as well as the image data. These control
sequences are the 6 bytes at the start and at the end of each image line, where an image line is defined
above. The frame start or status line, image and control sequence pixels, will also be qualified during this
mode.
QCK Exceptions
The output data from VV5300 can be formatted in many ways, as detailed in an earlier section of this
document. Under certain operating conditions the relationship between QCK and the output data is
compromised.
It is vital that the phase relationship between the output data stream and the QCK must be maintained from
line to line, for example ensuring that, if enabled, the line code byte is always qualified by the same edge of
the QCK, clearly only applicable when considering slow QCK qualification. It is known that there are an odd
number of pixel periods in each line of the frame. If the slow QCK is selected then clearly two pixels are
qualified during each QCK cycle resulting in the following modes of operation requiring special care: 4 bit
ADC 8 wire output, 8 bit ADC 8 wire output and 4 bit ADC 4 wire output. During the interline period, when the
data bus is outputting data fixed at FF (8bit ADC) or F (4bit ADC), the phase of the QCK is toggled, this will
occur during every interline period. For the 8bit 8wire or 4bit 4 wire options this change is a simple inversion.
The 4bit 8wire option is not quite as straightforward. During the interline period the QCK signal is changed
from its former state to 1 of 3 other states. In addition 2 out of the 4 possible states are video timing mode
dependent.
Please note that the number of nibbles/bytes qualified by the clocks described above, during the free running
QCK mode, will differ from the expected value, as follows:
cd34011-b.fm
17/10/97
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